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| ? 2007-2013 microchip technology inc. ds61145l-page 1 pic32 1.0 device overview this document defines th e programming specification for the pic32 families of 32-bit microcontrollers. this programming specification is designed to guide developers of external programmer tools. customers who are developing applications for pic32 devices should use development tools that already provide support for device programming. the major topics of discussion include: ? section 1.0 ?device overview? ? section 2.0 ?programming overview? ? section 3.0 ?programming steps? ? section 4.0 ?connecting to the device? ? section 5.0 ?ejtag vs. icsp? ? section 6.0 ?pseudo operations? ? section 7.0 ?entering 2-wire enhanced icsp mode? ? section 8.0 ?check device status? ? section 9.0 ?erasing the device? ? section 10.0 ?entering serial execution mode? ? section 11.0 ?downloading the programming executive (pe)? ? section 12.0 ?downloading a data block? ? section 13.0 ?initiating a flash row write? ? section 14.0 ?verify device memory? ? section 15.0 ?exiting programming mode? ? section 16.0 ?the programming executive? ? section 17.0 ?checksum? ? section 18.0 ?configuration memory and device id? ? section 19.0 ?tap controllers? ? section 20.0 ?ac/dc characteristics and timing requirements? ? appendix a: ?pic32 flash memory map? ? appendix b: ?hex file format? ? appendix c: ?revision history? 2.0 programmi ng overview all pic32 devices can be programmed through two primary methods: ? self-programming ? external tool programming the self-programming method requires that the target device already contains executable code with the logic necessary to complete the programming sequence. the external tool programming method does not require any code in the target device ? it can program all target devices with or without any executable code. this document describes the external tool programming method. refer to the individual sections of the ?pic32 family reference manual? and the specific device data sheet for more information about using the self-programming method. an external tool programm ing setup consists of an external programmer tool and a target pic32 device. figure 2-1 illustrates the block diagram view of the typical programming setup. the programmer tool is responsible for executing necessary programming steps and completing the programming operation. figure 2-1: programming system setup 2.1 devices with dual flash panel and dual boot regions the pic32mz embedded connectivity (ec) family of devices incorporate several features useful for field (self) programming of the device. these features include dual flash panels with dual boot regions, an aliasing scheme for the boot regions allowing auto- matic selection of boot code at start-up and a panel swap feature for program flash. the two flash panels and their associated boot regions can be erased and programmed separa tely. refer to section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? for a detailed explanation of these features. a development tool used for production programming will not be concerned about mo st of these features with the following exceptions: ? insuring that the swap bit (nvmcon<7>) is in the proper setting. the default setting is ? 0 ? for no swap of panels. the development tool should assume the default setting when generating source files for the programming tool. ? proper handling of the aliasing of the boot memory in the checksum calculatio n. the aliased sections will be duplicates of the fixed sections. see section 17.0 ?checksum? for more information on checksum calculations with aliased regions. target pic32 device cpu on-chip memory external programmer pic32 flash programming specification
pic32 ds61145l-page 2 ? 2007-2013 microchip technology inc. 2.2 programming interfaces all pic32 devices provide two physical interfaces to the external programmer tool: ? 2-wire in-circuit seri al programming? (icsp?) ? 4-wire joint test action group (jtag) see section 4.0 ?connecting to the device? for more information. either of these methods may use a downloadable programming executive (pe). the pe executes from the target device ram and hides device programming details from the programmer. it also removes overhead associated with data transfer and improves overall data throughput. microchip has developed a pe that is available for use with any external programmer (see section 16.0 ?the programming executive? for more information). section 3.0 ?programming steps? describes high- level programming steps, followed by a brief explanation of each step. detailed explanations are available in corresponding sections of this document. more information on progr amming commands, ejtag, and dc specifications are available in the following sections: ? section 18.0 ?configuration memory and device id? ? section 19.0 ?tap controllers? ? section 20.0 ?ac/dc characteristics and timing requirements? 2.3 enhanced jtag (ejtag) the 2-wire and 4-wire interfaces use the ejtag protocol to exchange data with the programmer. while this document provides a working description of this protocol as needed, advanced users are advised to refer to the ?ejtag specification? (md00047), which is available from mips technologies, inc. ( www.mips.com ). 2.4 data sizes per the ejtag specification, data sizes are defined as follows: ? one word: 32 bits ? one-half word: 16 bits ? one-quarter word: 8 bits ? one byte: 8 bits ? 2007-2013 microchip technology inc. ds61145l-page 3 pic32 3.0 programming steps all tool programmers must perform a common set of steps, regardless of the actual method being used. figure 3-1 shows the set of steps to program pic32 devices. figure 3-1: programming flow the following sequence lists the steps, with a brief explanation of each step. more detailed information about the steps is available in the following sections. 1. connect to the target device. to ensure successful programming, all required pins must be connected to appropriate signals. see section 4.0 ?connecting to the device? in this document fo r more information. 2. place the target device in programming mode. for 2-wire programming methods, the target device must be placed in a special programming mode (enhanced icsp?) before executing any other steps. see section 7.0 ?entering 2-wire enhanced icsp mode? for more information. 3. check the status of the device. step 3 checks the status of the device to ensure it is ready to receive information from the programmer. see section 8.0 ?check device status? for more information. 4. erase the target device. if the target memory block in the device is not blank, or if the device is code-protected, an erase step must be performed before programming any new data. see section 9.0 ?erasing the device? for more information. 5. enter programming mode. step 5 verifies that the device is not code- protected and boots the tap controller to start sending and receiving data to and from the pic32 cpu. see section 10.0 ?entering serial execution mode? for more information. 6. download the programming executive (pe). the pe is a small block of executable code that is downloaded into the ra m of the target device. it will receive and program the actual data. see section 11.0 ?downloading the programming executive (pe)? for more information. done exit programming mode verify device done initiate flash write download a data block download the pe (optional) enter serial exec mode erase device check device status start enter enhanced icsp? (only required for 2-wire) no yes note: for the 4-wire pr ogramming methods, step 2 is not required. note: if the programming method being used does not require the pe, step 6 is not required. pic32 ds61145l-page 4 ? 2007-2013 microchip technology inc. 7. download the block of data to program. all methods, with or wit hout the pe, must down- load the desired programming data into a block of memory in ram. see section 12.0 ?downloading a data block? for more information. 8. initiate flash write. after downloading each block of data into ram, the programming sequence must be started to program it into the target device?s flash memory. see section 13.0 ?initi ating a flash row write? for more information. 9. repeat steps 7 and 8 until all data blocks are downloaded and programmed. 10. verify the program memory. after all programming data and configuration bits are programmed, the target device memory should be read back and verified for the matching content. see section 14.0 ?verify device memory? for more information. 11. exit the programming mode. the newly programmed data is not effective until either power is removed and reapplied to the target device or an exit programming sequence is performed. see section 15.0 ?exiting programming mode? for more information. ? 2007-2013 microchip technology inc. ds61145l-page 5 pic32 4.0 connecting to the device the pic32 family provides two possible physical interfaces for connecting to and programming the memory contents ( figure 4-1 ). for all programming interfaces, the target device must be properly powered and all required signals must be connected. in addition, the interface must be enabled, either through its configuration bit, as in the case of the jtag 4-wire interface, or though a specia l initialization sequence, as is the case for the 2-wire icsp interface. the jtag interface is enabled by default in blank devices shipped from the factory. enabling icsp is described in section 7.0 ?entering 2-wire enhanced icsp mode? . figure 4-1: programming interfaces 4.1 4-wire interface one possible interface is the 4-wire jtag (ieee 1149.1) port. ta b l e 4 - 1 lists the required pin connections. this interface uses the following four communication lines to transfer data to and from the pic32 device being programmed: ? tck ? test clock input ? tms ? test mode select input ? tdi ? test data input ? tdo ? test data output these signals are described in the following four sections. refer to the specific device data sheet for the connection of the signals to the device pins. 4.1.1 test clock input (tck) tck is the clock that controls the updating of the tap controller and the shifting of data through the instruc- tion or selected data register(s). tck is independent of the processor clock with respect to both frequency and phase. 4.1.2 test mode select input (tms) tms is the control signal for the tap controller. this signal is sampled on the rising edge of tck. 4.1.3 test data input (tdi) tdi is the test data input to the instruction or selected data register(s). this signal is sampled on the rising edge of tck for some tap controller states. 4.1.4 test data output (tdo) tdo is the test data output from the instruction or data register(s). this signal changes on the falling edge of tck. tdo is only driven when data is shifted out, otherwise the tdo is tri-stated. table 4-1: 4-wire interface pins programmer 2-wire icsp? or 4-wire jtag + mclr , v dd , v ss pic32 device pin name pin type pin description mclr i programming enable envreg (2) i enable for on-chip voltage regulator v dd and av dd (1) p power supply v ss and av ss (1) p ground v cap p cpu logic filter capacitor connection tdi i test data in tdo o test data out tck i test clock tms i test mode state legend: i = input o = output p = power note 1: all power supply and ground pins must be connected, including analog supplies (av dd ) and ground (av ss ). 2: the envreg pin is not available on all devices. please refer to the ?pin diagrams? section in the specific device data sheet to determine availability. pic32 ds61145l-page 6 ? 2007-2013 microchip technology inc. 4.2 2-wire interface another possible interfac e is the 2-wire icsp port. table 4-2 lists the required pin connections. this interface uses the following two communication lines to transfer data to and from the pic32 device being programmed: ? pgecx ? serial program clock ? pgedx ? serial program data these signals are described in the following two sections. refer to the specific device data sheet for the connection of the signals to the chip pins. 4.2.1 serial program clock (pgec x ) pgecx is the clock that controls the updating of the tap controller and the shifting of data through the instruction or selected da ta register(s). pgecx is independent of the processor clock, with respect to both frequency and phase. 4.2.2 serial program data (pged x ) pgedx is the data input/outp ut to the instruction or selected data register(s), it is also the control signal for the tap controller. this signal is sampled on the falling edge of pgecx for some tap controller states. table 4-2: 2-wire interface pins device pin name programmer pin name pin type pin description mclr mclr p programming enable envreg (2) n/a i enable for on-chip voltage regulator v dd and av dd (1) v dd p power supply v ss and av ss (1) v ss p ground v cap n/a p cpu logic filter capacitor connection pgec1 pgec i primary programmi ng pin pair: serial clock pged1 pged i/o primary programmi ng pin pair: serial data pgec2 pgec i secondary programmi ng pin pair: serial clock pged2 pged i/o secondary programmi ng pin pair: serial data legend: i = input o = output p = power note 1: all power supply and ground pins must be connected, including analog supplies (av dd ) and ground (av ss ). 2: the envreg pin is not available on all devices. please refer to either the ?pin diagrams? or ?pin tables? section in the specific device data sheet to determine availability. ? 2007-2013 microchip technology inc. ds61145l-page 7 pic32 4.3 power requirements devices in the pic32 family are dual voltage supply designs. there is one supply for the core and another for peripherals and i/o pins. all devices contain an on-chip regulator for the lower voltage core supply to eliminate the need for an additional external regulator. there are three implementations of the on board regulator: ? the first version has an internal regulator that can be disabled using the envreg pin. when disabled, an external power supply must be used to power the core. if enabled, a low-esr filter capacitor must be connected to the v cap pin (see figure 4-2 ). ? the second version has an internal regulator that cannot be disabled. a low- esr filter capacitor must always be connected to the v cap pin. ? the third version has an internal regulator that cannot be disabled and does not require a filter capacitor please refer to section 20.0 ?ac/dc characteristics and timing requirements? and the ?electrical characteristics? chapters in the specific device data sheet for the power requirements for your device. figure 4-2: internal regulator enable/disable options v dd envreg v cap v ss pic32 3.3v (1) 1.8v (1) v dd envreg v cap v ss pic32 c efc 3.3v regulator enabled (2) regulator disabled (2) (10 ? f typical) note 1: these are typical operating voltages. refer to section 20.0 ?ac/dc characteristics and timing requirements? for the full operating ranges of v dd and v cap . 2: regulator enabled and regulator disabled mode are not available on all devices. please refer to the specific device data sheet to determine availability. (envreg tied to v dd ) (envreg tied to ground) pic32 ds61145l-page 8 ? 2007-2013 microchip technology inc. 5.0 ejtag vs. icsp programming is accomplished through the ejtag module in the cpu core. ejtag is connected to either the full set of jtag pins, or a reduced 2-wire to 4-wire ejtag interface for icsp mode. in both modes, programming of the pic32 flash memory is accomplished through the etap controller. the tap controller uses the tms pin to determine if instruction or data registers should be accessed in the shift path between tdi and tdo (see figure 5-1 ). the basic concept of ejtag that is used for programming is the use of a special memory area called dmseg (0xff200000 to 0xff2fffff), which is only available when the processor is running in debug mode. all instructions are serially shifted into an internal buffer, and then loaded into the instruction register and executed by the cpu. instructions are fed through the etap state machine in 32-bit groups. figure 5-1: tap controller tms tck tdo tdi tap controller instruction, data and control registers ? 2007-2013 microchip technology inc. ds61145l-page 9 pic32 5.1 programming interface figure 5-2 shows the basic programming interface in pic32 devices. descriptions of each interface block are provided in subsequent sections. figure 5-2: basic pic32 programming interface block diagram 5.1.1 etap this block serially feeds instructions and data into the cpu. 5.1.2 mtap in addition to the ejtag tap (etap) controller, the pic32 device uses a second proprietary tap controller for additional operations. the microchip tap (mtap) controller supports two instructions relevant to programming: mtap_command and tap switch instructions. see ta b l e 1 9 - 1 for a complete list of instructions. the mtap_command instruction provides a mechanism for a jtag probe to send commands to the device through its data register. the programmer sends commands by shifting in the mtap_command instruction through the sendcommand pseudo operation, and then sending mtap_command dr commands through xferdata pseudo operation (see table 19-2 for specific commands). the probe does not need to issue a mtap_command instruction for every command shifted into the data register. 5.1.3 2-wire to 4-wire this block converts the 2- wire icsp interface to the 4-wire jtag interface. 5.1.4 cpu the cpu executes instructions at 8 mhz through the internal oscillator. 5.1.5 flash controller the flash controller controls erasing and programming of the flash memory on the device. 5.1.6 flash memory the pic32 device flash memory is divided into two logical flash partitions cons isting of the boot flash memory (bfm) and program flash memory (pfm). the bfm begins at address 0x1fc00000, and the pfm begins at address 0x1d000000. each flash partition is divided into pages, which represent the smallest block of memory that can be erased. depending on the device, page sizes are 256 words (1024 bytes), 1024 words (4096 bytes), or 4096 words (16,384 bytes). row size indicates the numb er of words that are pro- grammed with the row program command. there are always 8 rows within a page ; therefore, devices with 256, 1024, and 4096 word page sizes have 32, 128, and 512 word row sizes, respectively. ta b l e 5 - 1 shows the pfm, bfm, row, and pa ge size of each device family. the highest memory locations of the bfm are reserved for the device configuration registers (see section 18.0 ?configuration memory and device id? for details). tms tck tdi tdo or pgecx pgedx etap cpu mtap 2-wire flash flash to 4-wire controller memory common v dd v ss mclr pic32 ds61145l-page 10 ? 2007-2013 microchip technology inc. table 5-1: code memory size pic32 device row size (words) page size (words) boot flash memory address (bytes) program flash memory address (bytes) pic32mx110f016b 32 256 0x1fc00000-0x1fc00bff (3 kb) 0x1d000000-0x1d003fff (16 kb) pic32mx110f016c 32 256 0x1fc00000-0x1fc00bff (3 kb) 0x1d000000-0x1d003fff (16 kb) pic32mx110f016d 32 256 0x1fc00000-0x1fc00b ff (3 kb) 0x1d000000-0x1d003fff (16 kb) pic32mx210f016b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d003fff (16 kb) pic32mx210f016c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d003fff (16 kb) pic32mx210f016d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d003fff (16 kb) pic32mx120f032b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx120f032c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx120f032d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx220f032b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx220f032c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx220f032d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1 d000000-0x1d007fff (32 kb) pic32mx320f032h 128 1024 0x1fc00000-0x1fc02 fff (12 kb) 0x1d000000-0x1d007fff (32 kb) pic32mx420f032h 128 1024 0x1fc00000-0x1fc02 fff (12 kb) 0x1d000000-0x1d007fff (32 kb) pic32mx130f064b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx130f064c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx130f064d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx230f064b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx230f064c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx230f064d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d0 00000-0x1d00ffff (64 kb) pic32mx320f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx330f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx430f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx534f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx564f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx664f064h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx330f064l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx430f064l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx534f064l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx564f064l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx664f064l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d00ffff (64 kb) pic32mx150f128b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx150f128c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx150f128d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx250f128b 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx250f128c 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx250f128d 32 256 0x1fc000 00-0x1fc00bff (3 kb) 0x1d 000000-0x1d01ffff (128 kb) pic32mx320f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx340f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx350f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx440f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx450f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx564f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx664f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx764f128h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx320f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx340f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) ? 2007-2013 microchip technology inc. ds61145l-page 11 pic32 pic32mx350f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx440f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx450f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx564f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx664f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx764f128l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d01ffff (128 kb) pic32mx340f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx350f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx440f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx450f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx575f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx675f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx775f256h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx350f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx360f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx450f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx460f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx575f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx675f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx775f256l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d03ffff (256 kb) pic32mx340f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx360f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx370f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx440f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx470f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx575f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx675f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx695f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx775f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx795f512h 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx360f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx370f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx460f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx470f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx575f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx675f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx695f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx775f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mx795f512l 128 1024 0x1fc0 0000-0x1fc02fff (12 kb) 0x1 d000000-0x1d07ffff (512 kb) pic32mz0256ece064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ece100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ece124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ece144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ecf064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ecf100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ecf124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) pic32mz0256ecf144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d03ffff (256 kb) table 5-1: code memory size (continued) pic32 device row size (words) page size (words) boot flash memory address (bytes) program flash memory address (bytes) pic32 ds61145l-page 12 ? 2007-2013 microchip technology inc. pic32mz0512ece064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ece100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ece124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ece144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ecf064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ecf100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ecf124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz0512ecf144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d07ffff (512 kb) pic32mz1024ece064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ece100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ece124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ece144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecf064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecf100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecf124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecf144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecg064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecg100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecg124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ecg144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ech064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ech100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ech124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz1024ech144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d0fffff (1024 kb) pic32mz2048ecg064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ecg100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ecg124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ecg144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ech064 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ech100 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ech124 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) pic32mz2048ech144 512 4096 0x1fc00000-0x1fc13 fff (80 kb) 0x1d000000- 0x1d1fffff (2048 kb) table 5-1: code memory size (continued) pic32 device row size (words) page size (words) boot flash memory address (bytes) program flash memory address (bytes) ? 2007-2013 microchip technology inc. ds61145l-page 13 pic32 5.2 4-wire jtag details the 4-wire interface uses standard jtag (ieee 1149.1-2001) interface signals. ? tck: test clock ? drives data in/out ? tms: test mode select ? selects operational mode ? tdi: test data in ? data into the device ? tdo: test data out ? data out of the device since only one data line is available, the protocol is necessarily serial (like spi). the clock input is at the tck pin. configuration is performed by manipulating a state machine bit by bit through the tms pin. one bit of data is transferred in and out per tck clock pulse at the tdi and tdo pins, respectively. different instruction modes can be loaded to read the chip id or manipulate chip functions. data presented to tdi must be valid for a chip-specific setup time before, and hold time, after the rising edge of tck. tdo data is valid for a chip-specific time after the falling edge of tck (refer to figure 5-3 ). figure 5-3: 4-wire jtag interface tms tdi tdo imsb ilsb ? 1 ? tck olsb omsb ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? pic32 ds61145l-page 14 ? 2007-2013 microchip technology inc. 5.3 2-wire icsp details in icsp mode, the 2-wire icsp signals are time multiplexed into the 2-wire to 4-wire block. the 2-wire to 4-wire block then converts the signals to look like a 4-wire jtag port to the tap controller. there are two possible modes of operation: ?4-phase icsp ?2-phase icsp 5.3.1 4-phase icsp in 4-phase icsp mode, the tdi, tdo and tms device pins are multiplexed onto pgedx in four clocks (see figure 5-4 ). the least significant bit (lsb) is shifted first; and tdi and tms are sampled on the falling edge of pgecx, while tdo is driven on the falling edge of pgecx. the 4-phase icsp mode is used for both read and write data transfers. 5.3.2 2-phase icsp in 2-phase icsp mode, the tms and tdi device pins are multiplexed into pgedx in two clocks (see figure 5-5 ). the lsb is shifted first; and tdi and tms are sampled on the falling edge of pgecx. there is no tdo output provided in th is mode. the 2-phase icsp mode was designed to accelerate 2-wire, write-only transactions. figure 5-4: 2-wire, 4-phase figure 5-5: 2-wire, 2-phase note: the packet is not actu ally executed until the first clock of the next packet. to enter 2-wire, 2-phase icsp mode, the tdoen bit (ddpcon<0>) must be set to ? 0 ?. tms tdi tdo ir4 ir0 ? 1 ? tck ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? x 1 pgecx pgedx ptdo = 1 tdi = ir0 tms = 0 ntdo = 0 tms tdi tdo ir4 ir0 ? 1 ? tck ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? x 1 pgecx pgedx tdi = ir0 tms = 0 ? 2007-2013 microchip technology inc. ds61145l-page 15 pic32 6.0 pseudo operations to simplify the description of programming details, all operations will be described using pseudo operations. there are several functions used in the pseudocode descriptions. these are used either to make the pseudocode more readable, to abstract implementation-specific behavior, or both. when passing parameters with pseudo operation, the following syntax will be used: ? 5?h0x03 ? send 5-bit hexadecimal value of 3 ? 6?b011111 ? send 6-bit binary value of 31 these functions are defined in this section, and include the following operations: ? setmode (mode) ? sendcommand (command) ?odata = xferdata (idata) ?odata = xferfastdata (idata) ?odata = xferinstruction (instruction) 6.1 setmode pseudo operation format: setmode (mode) purpose: to set the ejtag state machine to a specific state. description: the value of mode is clocked into the device on signal tms. tdi is set to a ? 0 ? and tdo is ignored. restrictions: none. example: setmode ( 6?b011111 ) figure 6-1: setmode 4-wire figure 6-2: setmode 2-wire tms tdi tdo ? 1 ? tck ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 0 ? mode = 6?b011111 pgedx pgecx tdi = 0 tdo = 1 tms = 1 tdi = 0 tms = 0 tdo = x mode = 6?b011111 pic32 ds61145l-page 16 ? 2007-2013 microchip technology inc. 6.2 sendcommand pseudo operation format: sendcommand (command) purpose: to send a command to select a specific tap register. description (in sequence): 1. the tms header is clocked into the device to select the shift ir state 2. the command is clocke d into the device on tdi while holding signal tms low. 3. the last most significant bit (msb) of the command is clocked in while setting tms high. 4. the tms footer is clocked in on tms to return the tap controller to the run/test idle state. restrictions: none. example: sendcommand (5?h0x07) figure 6-3: sendcommand 4-wire figure 6-4: sendcommand 2-wire (4-phase) tms tdi tdo imsb ? 1 ? tck ? 1 ? ? 1 ?? 1 ? ? 0 ?? 0 ? ? 0 ? x 1 ilsb tms header = 1100 command = 5?h0x07 command (msb) + tms = 1 tms footer = 10 tdi = 0 tms = 1 tms = 1 tdi = 0 tdo = x tdo = x tdi = imsb tdo = x tms = 0 tdi = ilsb tdo = x tms = 1 tms header = 1100 command (5?h0x07) + tms = 0 command (msb) + tms = 1 tms footer = 10 pgecx pgedx ? 2007-2013 microchip technology inc. ds61145l-page 17 pic32 6.3 xferdata pseudo operation format: odata = xferdata (idata) purpose: to clock data to and from the register selected by the command. description (in sequence): 1. the tms header is clocked into the device to select the shift dr state. 2. the data is clocked in/out of the device on tdi/tdo while holding signal tms low. 3. the last msb of the data is clocked in/out while setting tms high. 4. the tms footer is clocked in on tms to return the tap controller to the run/test idle state. restrictions: none. example: odata = xferdata (32?h0x12) figure 6-5: xferdata 4-wire figure 6-6: xferdata 2-wire (4-phase) tms tdi tdo imsb ? 1 ? tck ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? ilsb tms header = 100 data (32?h0x12) data (msb) + tms = 1 tms footer = 10 omsb olsb tdi = 0 tms = 0 tdo = olsb tdi = 0 tdo = x tms = 0 tdi = 0 tdo = x tms = 1 pgec pged tms header = 100 tdi = 0 tms = 0 tdo = x tdi = 0 tdo = x tms = 1 tms = 1 tdo = x tms = 0 tdi = ilsb tdo = olsb+1 tdi = imsb data (31?h0x12) + tms = 0 data (msb) + tms footer = 1 tms footer = 10 ... pic32 ds61145l-page 18 ? 2007-2013 microchip technology inc. 6.4 xferfastdata pseudo operation format: odata = xferfastdata (idata) purpose: to quickly send 32 bits of data in/out of the device. description (in sequence): 1. the tms header is clocked into the device to select the shift dr state. 2. the input value of the pracc bit, which is ? 0 ?, is clocked in. 3. tms footer = 10 is clocked in to return the tap controller to the run/test idle state. restrictions: the sendcommand ( etap_fastdata ) must be sent first to select the fastda ta register, as shown in example 6-1 . see table 19-4 for a detailed descriptions of commands. example 6-1: sendcommand figure 6-7: xferfastdata 4-wire figure 6-8: xferfastdata 2-wire (2-phase) note: for 2-wire (4-phase) ? on the last clock, the opracc bit is shifted out on tdo while clocking in the tms header. if the value of opracc is not ? 1 ?, the whole operation must be repeated. note: for 2-wire (4-phase) ? the tdo during this operation will be the lsb of output data. the rest of the 31 bits of the input data are clocked in and the 31 bits of output data are clocked out. for the last bit of the input data, the tms footer = 1 is set. note: the 2-phase xferdata is only used when talking to the pe. see section 16.0 ?the programming executive? for more information. // select the fastdata register sendcommand( etap_fastdata ) // send/receive 32-bit data odata = xferfastdata(32?h0x12) tms tdi tdo imsb ilsb ? 1 ? tck olsb omsb ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 1 ? tms header = 100 pracc data (32?h0x12) data (msb) + tms = 1 tms footer = 10 tdi = x tms = 1 tdi = x tdi = tms = 0 tdi = tms = 0 tdi = 0 tms = 1 tms header = 100 data (32?h0x12) tms footer = 10 ilsb pgedx pgecx pracc tms = 1 msb data (msb) tms = 1 ? 2007-2013 microchip technology inc. ds61145l-page 19 pic32 figure 6-9: xferfastdata 2-wire (4-phase) tdi = 0 tms = 0 tdo = opracc tdi = 0 tdo = x tms = 0 tdi = 0 tdo = x tms = 1 pgecx pgedx tms header = 100 tdi = 0 tms = 0 tdo = x tdi = 0 tdo = x tms = 1 tms = 1 tdo = x tms = 0 tdi = ilsb tdo = olsb+1 tdi = imsb data (31?h12) + tms = 0 data (msb) + tms footer = 1 tms footer = 10 tms = 0 tdi = 0 tdo = olsb pracc pic32 ds61145l-page 20 ? 2007-2013 microchip technology inc. 6.5 xferinstruction pseudo operation format: xferinstruction (instruction) purpose: to send 32 bits of data for the device to execute. description: the instruction is clocked into the device and then executed by cpu. restrictions: the device must be in debug mode. example 6-2: xferinstruction xferinstruction (instruction) { // select control register sendcommand(etap_control); // wait until cpu is ready // check if processor access bit (bit 18) is set do { controlval = xferdata(32?h0x0004c000); } while( pracc(contorlval<18>) is not ?1? ); // select data register sendcommand(etap_data); // send the instruction xferdata( instruction ); // tell cpu to execute instruction sendcommand(etap_control); xferdata(32?h0x0000c000); } ? 2007-2013 microchip technology inc. ds61145l-page 21 pic32 7.0 entering 2-wire enhanced icsp mode to use the 2-wire pgedx and pgecx pins for pro- gramming, they must be enabl ed. note that any pair of programming pins available on a particular device may be used, however, they must be used as a pair. pged1 must be used with pgec1, and so on. the following steps are required to enter 2-wire enhanced icsp mode: 1. the mclr pin is briefly driven high, then low. 2. a 32-bit key sequence is clocked into pgedx. 3. mclr is then driven high within a specified period of time and held. please refer to section 20.0 ?ac/dc characteristics and timing requirements? for timing requirements. the programming voltage applied to mclr is v ih , which is essentially v dd , in pic32 devices. there is no minimum time requirement for holding at v ih . after v ih is removed, an interval of at least p18 must elapse before presenting the key sequence on pgedx. the key sequence is a specific 32-bit pattern: ? 0100 1101 0100 0011 0100 1000 0101 0000 ? (the acronym ?mchp?, in ascii). the device will enter program/verify mode only if the key sequence is valid. the msb of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as the 2-wire enhanced icsp interface is to be maintained. an interval of at least time p19 and p7 must elapse before presenting data on pgedx. signals appearing on pgedx before p7 has elapsed will not be interpreted as valid. upon successful entry, the programming operations documented in subsequent se ctions can be performed. while in 2-wire enhanced icsp mode, all unused i/os are placed in the high-impedance state. figure 7-1: entering enhanced icsp? mode note: if using the 4-wire jtag interface, the following procedure is not necessary. mclr pgedx pgecx v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 0x4d434850 p1a p1b p18 p19 01001 0000 p7 v ih v ih p20 pic32 ds61145l-page 22 ? 2007-2013 microchip technology inc. 8.0 check device status before a device can be programmed, the programmer must check the status of t he device to ensure that it is ready to receive information. figure 8-1: check device status 8.1 4-wire interface four-wire jtag programming is a mission mode operation and therefore t he setup sequence to begin programing should be done while asserting mclr . holding the device in reset prevents the processor from executing instruct ions or driving ports. the following steps are required to check the device status using the 4-wire interface: 1. set mclr pin low. 2. setmode ( 6?b011111 ) to force the chip tap controller into run test/idle state. 3. sendcommand ( mtap_sw_mtap ). 4. sendcommand ( mtap_command ). 5. statusval = xferdata ( mchp_status ). 6. if cfgrdy (statusval<3>) is not ? 1 ? and fcbusy (statusval<2>) is not ? 0 ? goto step 5. 8.2 2-wire interface the following steps are required to check the device status using the 2-wire interface: 1. setmode ( 6?b011111 ) to force the chip tap controller into run test/idle state. 2. sendcommand ( mtap_sw_mtap ). 3. sendcommand ( mtap_command ). 4. statusval = xferdata ( mchp_status ). 5. if cfgrdy (statusval<3>) is not ? 1 ? and fcbusy (statusval<2>) is not ? 0 ?, goto step 4. setmode ( 6?b011111 ) sendcommand ( mtap_sw_mtap ) sendcommand ( mtap_command ) statusval = xferdata ( mchp_status ) fcbusy = 0 cfgrdy = 1 no set mclr low 4-wire done yes note: if using the 4-wire interface, the oscillator source, as selected by the configuration words, must be present to access flash memory. in an unprogrammed device, the oscillator source is the internal frc allow- ing for flash memory access. if the config- uration words have been reprogrammed selecting an external oscillator source then it must be present for flash memory access. see the ?special features? chapter in the specific device data sheet for details regarding oscillator selection using the configuration word settings. note: if cfgrdy and fcbusy do not come to the proper state within 10 ms, the sequence may have been executed incorrectly or the device is damaged. ? 2007-2013 microchip technology inc. ds61145l-page 23 pic32 9.0 erasing the device before a device can be programmed, it must be erased. the erase oper ation writes all ? 1 s? to the flash memory and prepares it to program a new set of data. once a device is erased, it can be verified by performing a ?blank check? operation. see section 9.1 ?blank check? for more information. the procedure for erasing program memory (program, boot, and configuration memory) consists of selecting the mtap and sending the mchp_erase command. the programmer then must wait for the erase operation to complete by reading and verifying bits in the mchp_status value. figure 9-1 illustrates the process for performing a chip erase. figure 9-1: erase device the following steps are required to erase a target device: 1. sendcommand ( mtap_sw_mtap ). 2. sendcommand ( mtap_command ). 3. xferdata ( mchp_erase ). 4. delay 1 ms. 5. statusval = xferdata ( mchp_status ). 6. if cfgrdy (statusval<3>) is not ? 1 ? and fcbusy (statusval<2>) is not ? 0 ?, goto to step 4. 9.1 blank check the term ?blank check? implies verifying that the device has been successfully erased and has no programmed memory locations. a blank or erased memory location always reads as ? 1 ?. the device configuration regi sters are ignored by the blank check. additionally, all unimplemented memory space should be ignored from the blank check. note: the device id memory locations are read- only and cannot be erased. therefore, chip erase has no effect on these memory locations. sendcommand ( mtap_command ) statusval = xferdata ( mchp_status ) fcbusy = 0 cfgrdy = 1 no sendcommand ( mtap_sw_mtap ) select mtap put mtap in command mode xferdata ( mchp_erase ) issue chip erase command read erase status done yes 1 millisecond delay note: the chip erase operation is a self-timed operation. if the fcbusy and cfgrdy bits do not become properly set within the specified chip erase time, the sequence may have been executed incorrectly or the device is damaged. pic32 ds61145l-page 24 ? 2007-2013 microchip technology inc. 10.0 entering serial execution mode before a device can be programmed, it must be placed in serial execution mode. the procedure for entering serial execution mo de consists of verifying that the device is not code-protected. if the device is code-protected, a chip erase must be performed. see section 9.0 ?erasing the device? for details. figure 10-1: entering serial execution mode 10.1 4-wire interface the following steps are required to enter serial execution mode: 1. sendcommand ( mtap_sw_mtap ). 2. sendcommand ( mtap_command ). 3. statusval = xferdata ( mchp_status ). 4. if cps (statusval<7>) is not ? 1 ?, the device must be erased first. 5. sendcommand ( mtap_sw_etap ). 6. sendcommand ( etap_ejtagboot ). 7. set mclr high. 10.2 2-wire interface the following steps are required to enter serial execution mode: 1. sendcommand ( mtap_sw_mtap ). 2. sendcommand ( mtap_command ). 3. statusval = xferdata ( mchp_status ). 4. if cps (statusval<7>) is not ? 1 ?, the device must be erased first. 5. xferdata ( mchp_assert_rst ). 6. sendcommand ( mtap_sw_etap ). 7. sendcommand ( etap_ejtagboot ). 8. sendcommand ( mtap_sw_mtap ). 9. sendcommand ( mtap_command ). 10. xferdata ( mchp_de_assert_rst ). 11. xferdata ( mchp_flash_enable ) ? this step is not required for pic32mz ec family devices . 12. sendcommand ( mtap_sw_etap ). select mtap sendcommand ( mtap_sw_mtap ) put mtap in command mode sendcommand ( mtap_command ) read code-protect status statusval = xferdata ( mchp_status ) cps = 1 cannot enter must erase first select etap sendcommand ( mtap_sw_etap ) put cpu in serial exec mode sendcommand ( etap_ejtagboot ) no 2-wire 4-wire set mclr high enable flash xferdata ( mchp_flash_en ) release reset xferdata ( mchp_de_assert_rst ) put mtap in command mode sendcommand ( mtap_command ) select mtap sendcommand ( mtap_sw_mtap ) assert reset xferdata ( mchp_assert_rst ) 2-wire yes select etap sendcommand ( mchp_sw_etap ) not required for pic32mz ec devices note: it is assumed that mclr has been driven low from the previous check device status step (see figure 8-1 ). ? 2007-2013 microchip technology inc. ds61145l-page 25 pic32 11.0 downloading the programming executive (pe) the pe resides in ram memory and is executed by the cpu to program the device. the pe provides the mechanism for the programmer to program and verify pic32 devices using a simple command set and communication protocol. there are several basic functions provided by the pe: ? read memory ? erase memory ? program memory ? blank check ? read executive firmware revision ? get the cyclic redundancy check (crc) of flash memory locations the pe performs the low-le vel tasks required for programming and verifying a device. this allows the programmer to program the device by issuing the appropriate commands and data. a detailed description for each command is provided in section 16.2 ?the pe command set? . the pe uses the device?s data ram for variable storage and program execution. after the pe has run, no assumptions should be made about the contents of data ram. after the pe is loaded into the data ram, the pic32 family can be programmed using the command set shown in ta b l e 1 6 - 1 . figure 11-1: downloading the pe loading the pe in the memory is a two step process: 1. load the pe loader in the data ram. (the pe loader loads the pe binary file in the proper loca- tion of the data ram, and when done, jumps to the programming exec and starts executing it.) 2. feed the pe binary to the pe loader. table 11-1 lists the steps that are required to download the pe. write the pe loader to ram load the pe table 11-1: download the pe operation operand step 1: initialize bmxcon to 0x1f0040. the instruction sequence executed by the pic32 core is: lui a0,0xbf88 ori a0,a0,0x2000 /* address of bmxcon */ lui a1,0x1f ori a1,a1,0x40 /* $a1 has 0x1f0040 */ sw a1,0(a0) /* bmxcon initialized */ xferinstruction 0x3c04bf88 xferinstruction 0x34842000 xferinstruction 0x3c05001f xferinstruction 0x34a50040 xferinstruction 0xac850000 step 2: initialize bmxdkpba to 0x800. the instruction sequence executed by the pic32 core is: li a1,0x800 sw a1,16(a0) xferinstruction 0x34050800 xferinstruction 0xac850010 step 3: initialize bmxdudba and bmxdupba to the value of bmxdrmsz. the instruction sequence executed by the pic32 core is: lw a1,64(a0) /* load bmxdmsz */ sw a1,32(a0) sw a1,48(a0) xferinstruction 0x8c850040 xferinstruction 0xac850020 xferinstruction 0xac850030 step 4: set up pic32 ram address for pe. the instruc- tion sequence executed by the pic32 core is: lui a0,0xa000 ori a0,a0,0x800 xferinstruction 0x3c04a000 xferinstruction 0x34840800 step 5: load the pe_loader. repeat this step (step 5) until the entire pe_loader is loaded in the pic32 memory. in the operands field, ? pic32 ds61145l-page 26 ? 2007-2013 microchip technology inc. step 6: jump to the pe_loader. the instruction sequence executed by the pic32 core is: lui t9,0xa000 ori t9,t9,0x800 jr t9 nop xferinstruction 0x3c19a000 xferinstruction 0x37390800 xferinstruction 0x03200008 xferinstruction 0x00000000 step 7: load the pe using the pe_loader. repeat the last instruction of this step (step 7) until the entire pe is loaded into the pic32 memory. in this step, you are given an intel ? hex format file of the pe that you will parse and transfer a number of 32-bit words at a time to the pic32 memory (refer to appendix b: ?hex file format? ). the instruction sequence executed by the pic32 is shown in the ?instruction? column of table 11-2 : pe loader op codes. sendcommand etap_fastdata xferfastdata pe_address (address of pe program block from pe hex file) xferfastdata pe_size (number of 32-bit words of the program block from pe hex file) xferfastdata pe software op code from pe hex file (pe instructions) step 8: jump to the pe. magic number (0xdead0000) instructs the pe_loader that the pe is completely loaded into the memory. when the pe_loader sees the magic number, it jumps to the pe. xferfastdata 0x00000000 xferfastdata 0xdead0000 table 11-1: download the pe (continued) operation operand table 11-2: pe loader op codes op code instruction 0x3c07dead lui a3, 0xdead 0x3c06ff20 lui a2, 0xff20 0x3c05ff20 lui al, 0xff20 herel: 0x8cc40000 lw a0, 0 (a2) 0x8cc30000 lw v1, 0 (a2) 0x1067000b beq v1, a3, ? 2007-2013 microchip technology inc. ds61145l-page 27 pic32 12.0 downloading a data block to program a block of data to the pic32 device, it must first be loaded into sram. 12.1 without the pe to program a block of memo ry without the use of the pe, the block of data must first be written to ram. this method requires the programmer to transfer the actual machine instructions with embedded (immediate) data for writing the block of data to the devices internal ram memory. figure 12-1: downloading data without the pe the following steps are required to download a block of data: 1. xferinstruction (op code). 2. repeat step 1 until the last instruction is transferred to cpu. table 12-1: download data op codes 12.2 with the pe when using the pe the steps in section 12.0 ?down- loading a data block? and section 13.0 ?initiating a flash row write? are handled in two single commands: row_program and program . the row_program command programs a single row of flash data, while the program command programs multiple rows of flash data. both of these commands are documented in section 16.0 ?the programming executive? . bufaddr = ram buffer address write 32-bit immediate increment bufaddr done no data to bufaddr op code instruction step 1: initialize sram base address to 0xa0000000. 3c10a000 lui $s0, 0xa000; step 2: write the entire row of data to be programmed into system sram. 3c08 3508 ae08 pic32 ds61145l-page 28 ? 2007-2013 microchip technology inc. 13.0 initiating a flash row write once a row of data has been downloaded into the device?s sram, the programming sequence must be initiated to write the block of data to flash memory. see ta b l e 1 3 - 1 for the op code and instructions for initiating a flash row write. 13.1 with the pe when using the pe, the data is immediately written to the flash memory from the sram. no further action is required. 13.2 without the pe flash memory write operations are controlled by the nvmcon register. programming is performed by setting nvmcon to select the type of write operation and initiating the programming sequence by setting the wr control bit (nvmcon<15>). figure 13-1: initiating flash write without the pe note: certain pic32 devices have available ecc memory. when the ecc feature is used, flash memory must be pro- grammed in groups of four 32-bit words using four, 32-bit word alignment. if ecc is dynamically used, the programming method determines when the feature is used. ecc is not enabled for words pro- grammed with the single word program- ming command. ecc is enabled for words programmed in groups of four, either with the quad word or row programming com- mands. failure to adhere to these meth- ods can result in ecc ded errors during run-time. see the specific device data sheet for details regarding ecc use and configuration. start operation unlock flash controller load addresses in nvm registers select write operation unprotect control registers done ? 2007-2013 microchip technology inc. ds61145l-page 29 pic32 the following steps are required to initiate a flash write: 1. xferinstruction (op code). 2. repeat step 1 until the last instruction is transferred to the cpu. table 13-1: initiate flash row write op codes for pic32 devices op code instruction step 1: all pic32 devices: initialize constants. registers a1, a2, and a3 are set for wren = 1 or nvmop<3:0> = 0011 , wr = 1 and wren = 1 , respectively. registers s1 and s2 are set for the unlock data values and s0 is initialized to ? 0 ?. 34054003 34068000 34074000 3c11aa99 36316655 3c125566 365299aa 3c100000 ori a1,$0,0x4003 ori a2,$0,0x8000 ori a3,$0,0x4000 lui s1,0xaa99 ori s1,s1,0x6655 lui s2,0x5566 ori s2,s2,0x99aa lui s0,0x0000 step 2: pic32mx devices only: set register a0 to the base address of the nvm register (0xbf80_f400). 3c04bf80 3484f400 lui a0,0xbf80 ori a0,a0,0xf400 step 2: pic32mz ec devices only: set register a0 to the base address of the nvm register (0xbf80_0600). register s3 is set for the value used to disable write protection in nvmbpb. 3c04bf80 34840600 34158080 lui a0,0xbf80 ori a0,a0,0x0600 ori s3,$0,0x8080 step 3: pic32mz ec devices only: unlock and disable boot flash write protection. ac910010 ac920010 ac950090 00000000 sw s1,16(a0) sw s2,16(a0) sw s3,144(a0) nop step 4: all pic32 devices: set the nvmaddr register with the address of the flash row to be programmed. 3c08 pic32 ds61145l-page 30 ? 2007-2013 microchip technology inc. 14.0 verify device memory the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. the configuration registers are verified with the rest of the code. 14.1 verifying memory with the pe memory verify is performed using the get_crc command, as shown in table 16-2 . figure 14-1: verifying memory with the pe the following steps are required to verify memory using the pe: 1. xferfastdata ( get_crc ). 2. xferfastdata ( start_address ). 3. xferfastdata (length). 4. valcksum = xferfastdata (32?h0x00). verify that valcksum matc hes the checksum of the copy held in the programmer?s buffer. 14.2 verifying memory without the pe reading from flash memory is performed by executing a series of read accesses from the fastdata register. table 19-4 shows the ejtag programming details, including the address and op code data for performing processor access operations. figure 14-2: verifying memory without the pe the following steps are required to verify memory: 1. xferinstruction (op code). 2. repeat step 1 until the last instruction is transferred to the cpu. 3. verify that valread matches the copy held in the programmer?s buffer. 4. repeat steps 1-3 for each memory location. table 14-1: verify device op codes note: because the configuration registers include the device code protection bit, code memory should be verified immedi- ately after writing (if code protection is enabled). this is because the device will not be readable or verifiable if a device reset occurs after the code-protect bit has been cleared. issue verify command receive response op code instruction step 1: initialize some constants. 3c13ff20 lui $s3, 0xff20 step 2: read memory location. 3c08 ? 2007-2013 microchip technology inc. ds61145l-page 31 pic32 15.0 exiting programming mode once a device has been properly programmed, the device must be taken out of programming mode to start proper execution of its new program memory contents. 15.1 4-wire interface exiting programming mode is done by removing v ih from mclr , as illustrated in figure 15-1 . the only requirement for exit is that an interval, p16, should elapse between the last clock and program signals before removing v ih . figure 15-1: 4-wire exit programming mode the following steps are required to exit programming mode: 1. setmode ( 5?b11111 ). 2. assert mclr . 3. remove power (if the device is powered). 15.2 2-wire interface exiting programming mode is done by removing v ih from mclr , as illustrated in figure 15-2 . the only requirement for exit is that an interval, p16, should elapse between the last clock and program signals on pgecx and pgedx before removing v ih . figure 15-2: 2-wire exit programming mode the following list provides the actual steps required to exit programming mode: 1. setmode ( 5?b11111 ). 2. assert mclr . 3. issue a clock pulse on pgecx. 4. remove power (if the device is powered). mclr v dd tck tms tdi tdo ? 1 ? ? 1 ? ? 0 ? p16 mclr v dd pgedx pgecx p16 p17 v ih v ih pgedx = input pic32 ds61145l-page 32 ? 2007-2013 microchip technology inc. 16.0 the programming executive 16.1 pe communication the programmer and the pe have a master-slave relationship, where the programmer is the master programming device and th e pe is the slave. all communication is initiated by the programmer in the form of a command. the pe is able to receive only one command at a time. correspondingly, after receiving and processing a command, the pe sends a single response to the programmer. 16.1.1 2-wire icsp ejtag rate in enhanced icsp mode, the pic32 family devices operate from the internal fast rc oscillator, which has a nominal frequency of 8 mhz. 16.1.2 communication overview the programmer and the pe communicate using the ejtag address, data and fast data registers. in partic- ular, the programmer transfers the command and data to the pe using the fastdata register. the programmer receives a response from the pe using the address and data registers. the pseudo operation of receiving a response is shown in the getperesponse pseudo operation below: format: response = getperesponse() purpose: enables the programmer to receive the 32-bit response value from the pe. example 16-1: getperesponse example the typical communication sequence between the programmer and the pe is shown in table 16-1 . the sequence begins when the programmer sends the command and optional additional data to the pe, and the pe carries out the command. when the pe has finished executing the command, it sends the response ba ck to the programmer. the response may contain more than one response. for example, if the programmer sent a read command, the response will contain the data read. table 16-1: communication sequence for the pe note: the programming executive (pe) is included with your installation of mplab ? ide. to download the appropriate pe file for your device, please visit the related product page on the microchip web site. operation operand step 1: send command and optional data from programmer to the pe. xferfastdata (command | data len) xferfastdata.. optional data.. step 2: programmer reads the response from the pe. getperesponse response getperesponse... response... word getperesponse() { word response; // wait until cpu is ready sendcommand(etap_control); // check if proc. access bit (bit 18) is set do { controlval=xferdata(32?h0x0004c000 ); } while( pracc(contorlval<18>) is not ?1? ); // select data register sendcommand(etap_data); // receive response response = xferdata(0); // tell cpu to execute instruction sendcommand(etap_control); xferdata(32?h0x0000c000); // return 32-bit response return response; } ? 2007-2013 microchip technology inc. ds61145l-page 33 pic32 16.2 the pe command set the pe command set is shown in ta b l e 1 6 - 2 . this table contains the op code, mnemonic, and short description for each command. functional details on each command are provided in section 16.2.3 ?row_program command? through section 16.2.14 ? change_cfg command? . the pe sends a response to the programmer for each command that it receives. th e response indicates if the command was processed correctly. it includes any required response data or error data. 16.2.1 command format all pe commands have a general format consisting of a 32-bit header and any required data for the command (see figure 16-1 ). the 32-bit header consists of a 16-bit op code field, which is used to identify the command, and a 16-bit command operand field. use of the operand field varies by command. the command in the op code field must match one of the commands in the command set that is listed in table 16-2 . any command received that does not match a command the list returns a nack response, as shown in ta b l e 1 6 - 3 . the pe uses the command operand field to determine the number of bytes to read from or to write to. if the value of this field is incorrect, the command is not be properly received by the pe. table 16-2: pe command set note: some commands have no operand infor- mation, however, the operand field must be sent and the programming executive will ignore the data. figure 16-1: command format 31 16 op code 15 0 operand (optional) 31 16 command data high (if required) 15 0 command data low (if required) op code mnemonic description 0x0 row_program (1) program one row of flash memory at the specified address. 0x1 read read n 32-bit words of memory starting from the specified address (n < 65,536). 0x2 program program flash memory starting at the specified address. 0x3 word_program (3) program one word of flash memory at the specified address. 0x4 chip_erase chip erase of entire chip. 0x5 page_erase erase pages of code memory from the specified address. 0x6 blank_check blank check code. 0x7 exec_version read the pe software version. 0x8 get_crc get the crc of flash memory. 0x9 program_cluster programs the specified number of bytes to the specified address. 0xa get_deviceid returns the hardware id of the device. 0xb change_cfg (2) used by the probe to set various configuration settings for the pe. 0xc get_checksum get the checksum of flash memory. 0xd quad_word_pgrm (4) program four words of flash memory at the specified address. note 1: refer to ta b l e 5 - 1 for the row size for each device. 2: this command is not available in pic32mx1xx/2xx devices. 3: on the pic32mz ec family devices, which incorporate ecc, the word_program command will not generate the ecc parity bits. reading a location programmed with the word_program command with ecc enabled will cause a ded fault. 4: this command is available on pic32mz ec family devices only. pic32 ds61145l-page 34 ? 2007-2013 microchip technology inc. 16.2.2 response format the pe response set is shown in ta b l e 1 6 - 3 . all pe responses have a general form at consisting of a 32-bit header and any required data for the response (see figure 16-2 ). 16.2.2.1 last_cmd field last_cmd is a 16-bit field in the first word of the response and indicates the command that the pe processed. it can be used to verify that the pe correctly received the command that the programmer transmitted. 16.2.2.2 response code the response code indicates whether the last command succeeded or failed, or if the command is a value that is not recognized. the response code values are shown in table 16-3 . 16.2.2.3 optional data the response header may be followed by optional data in case of certain commands such as read. the number of 32-bit words of optional data varies depending on the last command operation and its parameters. 16.2.3 row_program command the row_program command instructs the pe to program a row of data at a specified address. the data to be programm ed to memory, located in command words data_1 through data_n, must be arranged using the packed instruction word format shown in table 16-4 (this command expects an entire row of data). expected response (1 word): figure 16-4: row_program response figure 16-2: response format 31 16 last command 15 0 response code 31 16 data_high_1 15 0 data_low_1 31 16 data_high_n 15 0 data_low_n table 16-3: response values op code mnemonic description 0x0 pass command successfully processed 0x2 fail command unsuccessfully processed 0x3 nack command not known figure 16-3: row_program command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 data_high_1 15 0 data_low_1 31 16 data_high_n 15 0 data_low_n table 16-4: row _ program format field description op code 0x0 operand not used addr_high high 16 bits of 32-bit destination address addr_low low 16 bits of 32-bit destination address data_high_1 high 16 bits data word 1 data_low_1 low 16 bits data word 1 data_high_n high 16 bits data word 2 through n data_low_n low 16 bits data word 2 through n 31 16 last command 15 0 response code ? 2007-2013 microchip technology inc. ds61145l-page 35 pic32 16.2.4 read command the read command instructs the pe to read from memory the number of 32-bit words specified in the operand field starting from the 32-bit address specified by the addr_low and addr_high fields. this command can be used to read flash memory, as well as configuration words. all data returned in response to this command uses the packed data format that is shown in ta b l e 1 6 - 5 . expected response: figure 16-6: read response figure 16-5: read command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low table 16-5: read format field description op code 0x1 operand n number of 32-bit words to read (maximum of 65,535) addr_low low 16 bits of 32-bit source address addr_high high 16 bits of 32-bit source address 31 16 last command 15 0 response code 31 16 data_high_1 15 0 data_low_1 31 16 data_high_n 15 0 data_low_n note: reading unimplemented memory will cause the pe to reset. please ensure that only memory locations present on a particular device are accessed. pic32 ds61145l-page 36 ? 2007-2013 microchip technology inc. 16.2.5 program command the program command instructs the pe to program flash memory, including configuration words, starting from the 32-bit address specified in the addr_low and addr_high fields. a 32-bit length field specifies the number of bytes to program. the address must be aligned to a flash row size boundary and the length must be a multiple of a flash row size. flash row sizes are either 32 words (128 bytes) or 128 words (512 bytes). please refer to table 5-1 . there are three programming scenarios: 1. the length of the data to be programmed is the size of a single flash row. 2. the length of the data to be programmed is the size of two flash rows. 3. the length of the data to be programmed is larger than the size of two flash rows. when the data length is equal to 512 bytes, the pe receives the 512-byte block of data from the probe and immediately sends the response for this command back to the probe. the pe will respond for each row of data that it receives. if the data length of the command is equal to a single row, a single pe response is generated. if the data length is equal to two rows, the pe waits to receive both rows of data, and then sends back-to- back responses for each data row. if the data length is greater than two rows of data, the pe will send the response for the first row af ter receiving the first two rows of data. subsequent responses are sent after receiving subsequent data row packets. the responses will lag the data by one row. when the last row of data is received the pe will respond with back- to-back responses for the second-to-last data row followed by the last row. if the pe encounters an error in programming any of the blocks, it sends a failure status to the probe and aborts the program command. on receiving the failure status, the probe must stop sending data. the pe will not process any other data for this command from the probe. the process is illustrated in figure 16-9 . the response for this command is a little different than the response for other commands. the 16 msbs of the response contain the 16 lsbs of the destination address, where the last block is programmed. this helps the probe and the pe maintain proper synchronization of sending, and receiving, data and responses. expected response (1 word): figure 16-8: program response figure 16-7: program command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 length_high 15 0 length_low 31 16 data_high_1 15 0 data_low_1 31 16 data_high_n 15 0 data_low_n table 16-6: program format field description op code 0x2 operand not used addr_low low 16 bits of 32-bit destination address addr_high high 16 bits of 32-bit destination address length_low low 16 bits of length length_high high 16 bits length data_low_n low 16 bits data word 2 through n data_high_n high 16 bits data word 2 through n note: if the program command fails, the programmer should read the failing row using the read command from the flash memory. next, the programmer should compare the row received from flash memory to its local copy, word-by-word, to determine the address where flash programming fails. 31 16 lsb 16 bits of the destination address of last block 15 0 response code ? 2007-2013 microchip technology inc. ds61145l-page 37 pic32 figure 16-9: program command algorithm done receive status for row n receive status for row n-1 receive status for row 2 receive status for row 2 receive status for row 1 receive status (lsb 16 bits of destination address status value) send first row of data start send one row of data receive status for row 1 data is data is equal to a single row equal to two rows data is larger than two rows send first row of data send second row of data send second row of data send third row of data send nth row of data pic32 ds61145l-page 38 ? 2007-2013 microchip technology inc. 16.2.6 word_program command the word_program command instructs the pe to program a 32-bit word of da ta at the specified address. expected response (1 word): figure 16-11: word _ program response 16.2.7 chip_erase command the chip_erase command erases the entire chip, including the configuration block. after the erase is performed, the entire flash memory contains 0xffffffff. expected response (1 word): figure 16-13: chip_erase response figure 16-10: word_program command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 data_high 15 0 data_low table 16-7: word _ program format field description op code 0x3 operand not used addr_high high 16 bits of 32-bit destination address addr_low low 16 bits of 32-bit destination address data_high high 16 bits data word data_low low 16 bits data word 31 16 last command 15 0 response code figure 16-12: chip_erase command 31 16 op code 15 0 operand table 16-8: chip _ erase format field description op code 0x4 operand not used addr_low low 16 bits of 32-bit destination address addr_high high 16 bits of 32-bit destination address 31 16 last command 15 0 response code ? 2007-2013 microchip technology inc. ds61145l-page 39 pic32 16.2.8 page_erase command the page_erase command erases the specified number of pages of code memory from the specified base address. depending on the device, the specified base address must be a multiple of 0x400 or 0x100. after the erase is performed, all targeted words of code memory contain 0xffffffff. expected response (1 word): figure 16-15: page_erase response 16.2.9 blank_check command the blank_check command queries the pe to determine whether the contents of code memory and code-protect configuratio n bits (gcp and gwrp) are blank (contains all ? 1 ?s). expected response (1 word for blank device): figure 16-17: blank_check response figure 16-14: page _ erase command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low table 16-9: page _ erase format field description op code 0x5 operand number of pages to erase addr_low low 16 bits of 32-bit destination address addr_high high 16 bits of 32-bit destination address 31 16 last command 15 0 response code figure 16-16: blank_check command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 length_high 15 0 length_low table 16-10: blank _ check format field description op code 0x6 operand not used address address where to start the blank check length number of progra m memory locations to check in terms of bytes 31 16 last command 15 0 response code pic32 ds61145l-page 40 ? 2007-2013 microchip technology inc. 16.2.10 exec_version command exec_version queries for the version of the pe software stored in ram. expected response (1 word): figure 16-19: exec_version response 16.2.11 get_crc command get_crc calculates the crc of the buffer from the specified address to the specified length, using the table look-up method. the crc details are as follows: ? crc-ccitt, 16-bit ? polynomial: x^16+x^12+x^5+1, hex 0x00011021 ? seed: 0xffff ? most significant byte (msb) shifted in first expected response (2 words): figure 16-21: get_crc response figure 16-18: exec_version command 31 16 op code 15 0 operand table 16-11: exec _ version format field description op code 0x7 operand not used 31 16 last command 15 0 version number note 1: in the response, only the crc least significant 16 bits are valid. 2: the pe will automatically determine if the hardware crc is available and use it by default. the hardware crc is not used on pic32mx1xx/2xx devices. figure 16-20: get_crc command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 length_high 15 0 length_low table 16-12: get _ crc format field description op code 0x8 operand not used address address where to start calculating the crc length length of buffer on which to calculate the crc, in number of bytes 31 16 last command 15 0 response code 31 16 crc_high 15 0 crc_low ? 2007-2013 microchip technology inc. ds61145l-page 41 pic32 16.2.12 program_cluster command program_cluster programs the specified number of bytes to the specified address. the address must be 32-bit aligned, and the number of bytes must be a multiple of a 32-bit word. expected response (1 word): figure 16-23: program_cluster response 16.2.13 get_deviceid command the get_deviceid command returns the hardware id of the device. expected response (1 word): figure 16-25: get_deviceid response figure 16-22: program_cluster command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 length_high 15 0 length_low table 16-13: program _ cluster format field description op code 0x9 operand not used address start address for programming length length of area to program in number of bytes note: if the program_cluster command fails, the programmer should read the failing row using the read command from the flash memory. next, the programmer should compare the row received from flash memory to its local copy word-by-word to determine the address where flash programming fails. 31 16 last command 15 0 response code figure 16-24: get_deviceid command 31 16 op code 15 0 operand table 16-14: get_deviceid format field description op code 0xa operand not used 31 16 last command 15 0 device id pic32 ds61145l-page 42 ? 2007-2013 microchip technology inc. 16.2.14 change_cfg command expected response (1 word): figure 16-27: change_cfg response 16.2.15 get_checksum command expected response (1 word): figure 16-29: get_checksum response change_cfg is used by the probe to set various con- figuration settings for the pe. currently, the single con- figuration setting determines which of the following calculation methods the pe should use: ? software crc calculation method ? hardware calculation method figure 16-26: change_cfg command 31 16 op code 15 0 operand 31 16 crcflag_high 15 0 crcflag_low table 16-15: change _ cfg format field description op code 0xb operand not used crcflag if the value is ? 0 ?, the pe uses the software crc calculation method. if the value is ? 1 ?, the pe uses the hardware crc unit to calculate the crc. 31 16 last command 15 0 response code note: the command, change_cfg , is not available in pic32mx1xx/2xx devices. get_checksum returns the sum of all the bytes starting at the address ar gument up to the length argument. the result is a 32-bit word. figure 16-28: change_cfg command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 length_high 15 0 length_low table 16-16: get_checksum format field description op code 0x0c operand not used addr_high high-order 16 bits of the 32-bit starting address of the data to calculate the checksum for. addr_low low-order 16 bits of the 32-bit starting address of the data to calculate the checksum for. length_high high-order 16 bits of the 32-bit length of data to calculate the checksum for in bytes. length_low low-order 16 bits of the 32-bit length of data to calculate the checksum for in bytes. 31 16 last command 15 0 response code 31 16 checksum_high 15 0 checksum_low ? 2007-2013 microchip technology inc. ds61145l-page 43 pic32 16.2.16 quad_word_program command expected response (1 word): figure 16-31: quad_word_program response quad_word_program instructs the pe to program four, 32-bit words at the specified address. the address must be an aligned four word boundary (bits 0- 1 must be ? 0 ?). if not, the command will return a fail response value and no data will be programmed. figure 16-30: quad_word_program command 31 16 op code 15 0 operand 31 16 addr_high 15 0 addr_low 31 16 data0_high 15 0 data0_low 31 16 data1_high 15 0 data1_low 31 16 data2_high 15 0 data2_low 31 16 data3_high 15 0 data3_low table 16-17: quad_word_program format field description op code 0x0c operand not used addr_high high-order 16 bits of the 32-bit starting address. addr_low low -order 16 bits of the 32-bit starting address. data0_high high-order 16 bits of data word 0. data0_low low-order 16 bits of data word 0. data1_high high-order 16 bits of data word 1. data1_low low-order 16 bits of data word 1. data2_high high-order 16 bits of data word 2. data2_low low-order 16 bits of data word 2. data3_high high-order 16 bits of data word 3. data3_low low-order 16 bits of data word 3. 31 16 last command 15 0 response code pic32 ds61145l-page 44 ? 2007-2013 microchip technology inc. 17.0 checksum 17.1 theory the checksum is calculated as the 32-bit summation of all bytes (8-bit quantities) in program flash, boot flash (except device configuration words), the device id register with applicable ma sk, and the device configu- ration words with applicabl e masks. next, the 2?s complement of the summation is calculated. this final 32-bit number is presented as the checksum. 17.2 mask values the mask value of a device configuration is calculated by setting all the unimplemented bits to ? 0 ? and all the implemented bits to ? 1 ?. for example, register 17-1 shows the devcfg0 reg- ister of the pic32mx360f512l device. the mask value for this register is: mask_value_devcfg0 = 0x110ff00b table 17-1 lists the mask values of the four device con- figuration registers and device id registers to be used in the checksum calculations. register 17-1: devcfg0 regi ster of pic32mx360f512l bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r/p-1 r-1 r-1 r-1 r/p-1 ? ? ?cp ? ? ?bwp 23:16 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? pwp19 pwp18 pwp17 pwp16 15:8 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r-1 r-1 r-1 pwp15 pwp14 pwp13 pwp12 ? ? ? ? 7:0 r-1 r-1 r-1 r-1 r/p-1 r-1 r/p-1 r/p-1 ? ? ? ? icesel ? debug<1:0> legend: p = programmable bit r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2007-2013 microchip technology inc. ds61145l-page 45 pic32 table 17-1: device configuration re gister mask values of currently supported pic32 devices device devcfg0 devcfg1 devcfg2 devcfg3 devid all pic32mx1xx family 0x1100fc1f 0x03dff7a7 0x0070077 0xf0000000 0x0fffffff all pic32mx2xx family 0x1100fc1f 0x03dff7a7 0x0078777 0xf0000000 0x0fffffff all pic32mx320/340/360 family 0x110ff00b 0x009ff7a7 0x00070077 0x00000000 0x000ff000 all pic32mx330/350/370 family 0x110ff01f 0x03dff7a7 0x00070077 0x30c70000 0x00ffffff all pic32mx420/440/460 family 0x110ff00b 0x009ff7a7 0x00078777 0x00000000 0x000ff000 all pic32mx430/450/470 family 0x110ff01f 0x03dff7a7 0x00078777 0xf0c70000 0x00ffffff all pic32mz ec family 0x7fffffff 0xffffffff 0xffffffff 0xffff0000 0x0fffffff pic32mx534f064h 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx534f064l 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx564f064h 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx564f064l 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx564f128h 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx564f128l 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x0ffff000 pic32mx575f256h 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x000ff000 pic32mx575f256l 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x000ff000 pic32mx575f512h 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x000ff000 pic32mx575f512l 0x110ff00f 0x009ff7a7 0x00078777 0xc4070000 0x000ff000 pic32mx664f064h 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x0ffff000 pic32mx664f064l 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x0ffff000 pic32mx664f128h 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x0ffff000 pic32mx664f128l 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x0ffff000 pic32mx675f256h 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx675f256l 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx675f512h 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx675f512l 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx695f512h 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx695f512l 0x110ff00f 0x009ff7a7 0x00078777 0xc3070000 0x000ff000 pic32mx764f128h 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x0ffff000 pic32mx764f128l 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x0ffff000 pic32mx775f256h 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32mx775f256l 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32mx775f512h 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32mx775f512l 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32mx795f512h 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32mx795f512l 0x110ff00f 0x009ff7a7 0x00078777 0xc7070000 0x000ff000 pic32 ds61145l-page 46 ? 2007-2013 microchip technology inc. 17.3 algorithm an example of a high-level algorithm for calculating the checksum for a pic32 device is illustrated in figure 17-1 to demonstrate one method to derive a checksum. this is merely an example of how the actual calculations can be accomplished, the method that is ultimately used is left to the discretion of the software developer. as stated earlier, the pic32 checksum is calculated as the 32-bit summation of all bytes (8-bit quantities) in program flash, boot flash (except device configuration words), the device id register with applicable mask, and the device configuration words with applicable masks. next, the 2?s complement of the summation is calculated. this final 32-bit number is presented as the checksum. the mask values of the device configuration and device id registers are de rived as described in the previous section, section 17.2 ?mask values? . another noteworthy point is that the last four 32-bit quantities in boot flash ar e the device configuration registers. an arithmetic a nd operation of these device configuration register values is performed with the appropriate mask value, before adding their bytes to the checksum. similarly, an arithmetic and operation of the device id register is performed with the appropriate mask value, before adding its bytes to the checksum. figure 17-1: high-level algori thm for checksum calculation pic32_checksum read program flash, boot flash (including devcfg registers) and devid register in tempbuffer apply devcfg and devid masks to appropriate locations in tempbuffer tmpchecksum (32-bit quantity) = 0 finish processing all bytes (8-bit quantities) in tempbuffer? tmpchecksum = tempchecksum + current byte value (8-bit quantity) in tmpbuffer checksum (32-bit quantity) = 2?s complement of tmpchecksum done no yes ? 2007-2013 microchip technology inc. ds61145l-page 47 pic32 the formula to calculate the checksum for a pic32 device is provided in equation 17-1 . equation 17-1: checksum formula 17.4 example of checksum calculation the following five sectio ns demonstrate a checksum calculation for the pic32mx360f512l device using equation 17-1 . the following assumptions are made for the purpose of this checksum calculation example: ? program flash and boot flash are in the erased state (all bytes are 0xff) ? device configuration is in the default state of the device (no configuration changes are made) to begin, each item on the right-hand side of the equa- tion (pf, bf, dcr, dir) is individually calculated. after those values have been derived, the final value of the checksum can be determined. 17.4.1 calculating for ?pf? in the checksum formula the size of program flash is 512 kb, which equals 524288 bytes. since the program flash is assumed to be in erased state, the value of ?pf? is resolved through the following calculation: pf = 0xff + 0xff + ? 524288 times pf = 0x7f80000 (32-bit number) 17.4.2 calculating for ?bf? in the checksum formula the size of the boot flash is 12 kb, which equals 12288 bytes. however, the last 16 bytes are device configuration registers, which are treated separately. therefore, the numb er of bytes in boot flash that we consider in this step is 12272. since the boot flash is assumed to be in erased state, the value of ?bf? is resolved through the following calculation: bf = 0xff + 0xff + ? 12272 times bf = 0x002fc010 (32-bit number) 17.4.3 calculating for ?dcr? in the checksum formula since the device configuration registers are left in their default state, the value of the appropriate devcfg register ? as read by the pic32 core, its respective mask value, the value derived from applying the mask, and the 32-bit summation of bytes (all as shown in table 17-2 ) provide the total of the 32-bit summation of bytes. from table 17-2 , the value of ?dcr? is: dcr = 0x000003d6 (32-bit number) checksum 2 ? s complement pf bf dcr dir ++ + ?? = dcr 3 ? x 0 = 32-bit summation of bytes mask devcfgx & devcfgx ?? = dir 32-bit summation of bytes mask devid & devid ?? = where, pf = 32-bit summation of all bytes in program flash bf = 32-bit summation of all bytes in boot fl ash, except device configuration registers mask devcfgx = mask value from table 17-1 mask devid = mask value from table 17-1 table 17-2: dcr calculation example register por default value mask por default value & mask 32-bit summation of bytes devcfg0 0x7fffffff 0x110ff00b 0x110ff00b 0x0000011b devcfg1 0xffffffff 0x009ff7a7 0x009ff7a7 0x0000023d devcfg2 0xffffffff 0x00070077 0x00070077 0x0000007e devcfg3 0xffffffff 0x00000000 0x00000000 0x00000000 total of the 32-bit summation of bytes = 0x000003d6 pic32 ds61145l-page 48 ? 2007-2013 microchip technology inc. 17.4.4 calculating for ?dir? in the checksum formula the value of device id r egister, its mask value, the value derived from applying the mask, and the 32-bit summation of bytes are shown in table 17-3 . from table 17-3 , the value of ?dir? is: dir = 0x00000083 (32-bit number.) 17.4.5 completing the pic32 checksum calculation the values derived in previous sections (pf, bf, dcr, dir) are used to calculate the checksum value. first, perform the 32-bit summation of the pf, bf, dcr and dir as derived in previous sections and store it in a variable, called temp , as shown in example 17-1 . example 17-1: checksum calculation process 17.4.6 checksum values while device is code-protected since the device configuration words are not readable while the pic32 devices are in code-protected state, the checksum values are zeros for all devices. table 17-3: dir calculation example register por default value mask por default value & mask 32-bit summation of bytes devid 0x00938053 0x000ff000 0x00038000 0x00000083 1. first, temp = pf + bf + dcr + dir, which translates to: temp = 0x7f80000 + 0x002fc010 + 0x000003d6 + 0x00000083 2. adding all four values results in temp being equal to 0x0827c406 3. next, the 1?s complement of temp , called temp1 , is calculated: temp1 = 1?s complement ( temp ), which is now equal to 0xf7d83b96 4. finally, the 2?s complement of temp is the checksum: checksum = 2?s complement ( temp ), which is checksum = temp1 + 1, resulting in 0xf7d83b97 ? 2007-2013 microchip technology inc. ds61145l-page 49 pic32 18.0 configuration memory and device id pic32 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these features are configurable through specific configuration bits for each device. refer to the ?special features? chapter in the specific device data sheet for a full list of available features, configuration bits, and the device id register. see ta b l e 1 8 - 4 for a full list of device id and revision number for specific devices. 18.1 device configuration in pic32 devices, the configuration words select various device configurations that ar e set at device reset prior to execution of any code. these values are located at the highest locations of boot fl ash memory (bfm) and since they are part of the program memory, are included in the programming file along with executable code and pro- gram constants. the names and locations of these con- figuration words are listed in table 18-1 through table 18-3 . additionally, table 18-3 includes configuration words for pic32mz ec family devic es with dual boot and dual panel flash. refer to section 3. ?memory organiza- tion? (ds61115) in the ?pic32 family reference manual? for a detailed description of the dual boot regions. table 18-1: devcfg locations table 18-2: devcfg locations for pic32mx1x0 and pic32mx20x devices only on power-on reset (por), or any reset, the configu- ration words are copied from the boot flash memory to their corresponding configuration registers. a configu- ration bit can only be programmed = 0 (unprogrammed state = 1 ). during programming, a configuration word can be programmed a maximum of two times for pic32mx devices and only one time for pic32mz ec devices before a page erase must be performed. after programming the configuration words, a device reset will cause the new values to be loaded into the configuration registers. bec ause of this, the programmer should program the configuration words just prior to ver- ification of the device. the final step is programming the code protection configuration word. these configuration words determine the oscillator source. if using the 2-wire enhanced icsp mode the configuration words are ignored and the device will always use the frc; however, in 4-wire mode this is not the case. if an oscillator source is selected by the configuration words that is not present on the device after reset, the programmer will not be able to perform flash operations on the device after it is reset. see the ?special features? chapter in the specific device data sheet for details regarding oscillator selection using the configuration words. configuration word physical address devcfg0 0x1fc02ffc devcfg1 0x1fc02ff8 devcfg2 0x1fc02ff4 devcfg3 0x1fc02ff0 configuration word physical address devcfg0 0x1fc00bfc devcfg1 0x1fc00bf8 devcfg2 0x1fc00bf4 devcfg3 0x1fc00bf0 pic32 ds61145l-page 50 ? 2007-2013 microchip technology inc. table 18-3: configuration word locations for pic32mz ec family devices configuration word (see note 1) register physical address fixed boot region 1 fixed boot region 2 active boot alias region (see note 2) inactive boot alias region (see note 2) boot sequence number 0x1fc4fff0 0x1fc6fff0 0x1fc0fff0 0x1fc2fff0 code protection 0x1fc4ffd0 0x1fc6ffd0 0x1fc0ffd0 0x1fc2ffd0 devcfg0 0x1fc4ffcc 0x1fc6ffcc 0x1fc0ffcc 0x1fc2ffcc devcfg1 0x1fc4ffc8 0x1fc6ffc8 0x1fc0ffc8 0x1fc2ffc8 devcfg2 0x1fc4ffc4 0x1fc6ffc4 0x1fc0ffc4 0x1fc2ffc4 devcfg3 0x1fc4ffc0 0x1fc6ffc0 0x1fc0ffc0 0x1fc2ffc0 alternate boot sequence number 0x1fc4 ff70 0x1fc6ff70 0x1fc0ff70 0x1fc2ff70 alternate code protection 0x1fc4ff50 0x1fc6ff50 0x1fc0ff50 0x1fc2ff50 alternate devcfg0 0x1fc4ff4c 0x1fc6ff4c 0x1fc0ff4c 0x1fc2ff4c alternate devcfg1 0x1fc4ff48 0x1fc6ff48 0x1fc0ff48 0x1fc2ff48 alternate devcfg2 0x1fc4ff44 0x1fc6ff44 0x1fc0ff44 0x1fc2ff44 alternate devcfg3 0x1fc4ff40 0x1fc6ff40 0x1fc0ff40 0x1fc2ff40 note 1: each of the following configuration word groups should be programmed using the quad_word_program command to insure proper ecc configuration: ? boot sequence number (single quad word programming operation) ? code protection (single quad word programming operation) ? devcfg3, devcfg2, devcfg1, and devcfg0 (single quad word programming operation) ? alternate boot sequence number (sin gle quad word programming operation) ? alternate code protection (single quad word programming operation) ? alternate devcfg3, alternate devcfg2, alternat e devcfg1, and alternate devcfg0 (single quad word programming operation) 2: active/inactive boot alias selecti ons are assumed for an unprogrammed device where fixed region 1 is active and fixed region 2 is inactive. refer to section 3. ?memory organization? (ds61115) for a detailed description of the alias boot regions. ? 2007-2013 microchip technology inc. ds61145l-page 51 pic32 18.1.1 configuration register protection to prevent inadvertent configuration bit changes dur- ing code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it can not be written to again. changing a device configuration requires changing the configuration data in the boot flash memory, and cycling power to the device. to ensure integrity of the 128-bit data, a comparison is made between each configuration bit and its stored complement continuously. if a mismatch is detected, a configuration mismatch reset is generated, which causes a device reset. table 18-4: device ids and revision device devid register value revision id and silicon revision pic32mx110f016b 0x04a07053 0x0 ? a0 revision pic32mx110f016c 0x04a09053 pic32mx110f016d 0x04a0b053 pic32mx120f032b 0x04a06053 pic32mx120f032c 0x04a08053 pic32mx120f032d 0x04a0a053 pic32mx130f064b 0x04d07053 pic32mx130f064c 0x04d09053 pic32mx130f064d 0x04d0b053 pic32mx150f128b 0x04d06053 pic32mx150f128c 0x04d08053 pic32mx150f128d 0x04d0a053 pic32mx210f016b 0x04a01053 pic32mx210f016c 0x04a03053 pic32mx210f016d 0x04a05053 pic32mx220f032b 0x04a00053 pic32mx220f032c 0x04a02053 pic32mx220f032d 0x04a04053 pic32mx230f064b 0x04d01053 pic32mx230f064c 0x04d03053 pic32mx230f064d 0x04d05053 pic32mx250f128b 0x04d00053 pic32mx250f128c 0x04d02053 pic32mx250f128d 0x04d04053 pic32mx330f064h 0x05600053 pic32mx330f064l 0x05601053 pic32mx430f064h 0x05602053 pic32mx430f064l 0x05603053 pic32mx350f128h 0x0570c053 pic32mx350f128l 0x0570d053 pic32mx450f128h 0x0570e053 pic32mx450f128l 0x0570f053 pic32mx350f256h 0x05704053 pic32mx350f256l 0x05705053 pic32mx450f256h 0x05706053 pic32mx450f256l 0x05707053 pic32mx370f512h 0x05808053 pic32mx370f512l 0x05809053 pic32mx470f512h 0x0580a053 pic32mx470f512l 0x0580b053 pic32 ds61145l-page 52 ? 2007-2013 microchip technology inc. pic32mx360f512l 0x0938053 0x3 ? b2 revision 0x4 ? b3 revision 0x5 ? b4 revision 0x5 ? b6 revision pic32mx360f256l 0x0934053 pic32mx340f128l 0x092d053 pic32mx320f128l 0x092a053 pic32mx340f512h 0x0916053 pic32mx340f256h 0x0912053 pic32mx340f128h 0x090d053 pic32mx320f128h 0x090a053 pic32mx320f064h 0x0906053 pic32mx320f032h 0x0902053 pic32mx460f512l 0x0978053 pic32mx460f256l 0x0974053 pic32mx440f128l 0x096d053 pic32mx440f256h 0x0952053 pic32mx440f512h 0x0956053 pic32mx440f128h 0x094d053 pic32mx420f032h 0x0942053 pic32mx534f064h 0x4400053 0x0 ? a0 revision 0x1 ? a1 revision pic32mx534f064l 0x440c053 pic32mx564f064h 0x4401053 pic32mx564f064l 0x440d053 pic32mx564f128h 0x4403053 pic32mx564f128l 0x440f053 pic32mx575f256h 0x4317053 pic32mx575f256l 0x4333053 pic32mx575f512h 0x4309053 pic32mx575f512l 0x430f053 pic32mx664f064h 0x4405053 pic32mx664f064l 0x4411053 pic32mx664f128h 0x4407053 pic32mx664f128l 0x4413053 pic32mx675f256h 0x430b053 pic32mx675f256l 0x4305053 pic32mx675f512h 0x430c053 pic32mx675f512l 0x4311053 pic32mx695f512h 0x4325053 pic32mx695f512l 0x4341053 pic32mx764f128h 0x440b053 pic32mx764f128l 0x4417053 pic32mx775f256h 0x4303053 pic32mx775f256l 0x4312053 pic32mx775f512h 0x430d053 pic32mx775f512l 0x4306053 pic32mx795f512h 0x430e053 pic32mx795f512l 0x4307053 table 18-4: device ids and revision (continued) device devid register value revision id and silicon revision ? 2007-2013 microchip technology inc. ds61145l-page 53 pic32 pic32mz0256ece064 0x05100053 0x0 ? a0 revision pic32mz0256ece100 0x0510a053 pic32mz0256ece124 0x05114053 pic32mz0256ece144 0x0511e053 pic32mz0256ecf064 0x05105053 pic32mz0256ecf100 0x0510f053 pic32mz0256ecf124 0x05119053 pic32mz0256ecf144 0x05123053 pic32mz0512ece064 0x05101053 pic32mz0512ece100 0x0510b053 pic32mz0512ece124 0x05115053 pic32mz0512ece144 0x0511f053 pic32mz0512ecf064 0x05106053 pic32mz0512ecf100 0x05110053 pic32mz0512ecf124 0x0511a053 pic32mz0512ecf144 0x05124053 pic32mz1024ece064 0x05102053 pic32mz1024ece100 0x0510c053 pic32mz1024ece124 0x05116053 pic32mz1024ece144 0x05120053 pic32mz1024ecf064 0x05107053 pic32mz1024ecf100 0x05111053 pic32mz1024ecf124 0x0511b053 pic32mz1024ecf144 0x05125053 pic32mz1024ecg064 0x05103053 pic32mz1024ecg100 0x0510d053 pic32mz1024ecg124 0x05117053 pic32mz1024ecg144 0x05121053 pic32mz1024ech064 0x05108053 pic32mz1024ech100 0x05112053 pic32mz1024ech124 0x0511c053 pic32mz1024ech144 0x05126053 pic32mz2048ecg064 0x05104053 pic32mz2048ecg100 0x0510e053 0x0 ? a0 revision pic32mz2048ecg124 0x05118053 pic32mz2048ecg144 0x05122053 pic32mz2048ech064 0x05109053 pic32mz2048ech100 0x05113053 pic32mz2048ech124 0x0511d053 pic32mz2048ech144 0x05127053 table 18-4: device ids and revision (continued) device devid register value revision id and silicon revision pic32 ds61145l-page 54 ? 2007-2013 microchip technology inc. 18.2 device code protection bit (cp) the pic32 family of devic es feature code protec- tion, which when enabled, prevents reading of flash memory by an external programming device. once code protection is enabled, it can only be disabled by erasing the device with the chip erase command ( mchp_erase ). when programming a device that has opted to uti- lize code protection, the programming device must perform verification prior to enabling code protec- tion. enabling code protection should be the last step of the programming proces s. location of the code protection enable bits vary by device. refer to the ?special features? chapter in the specific device data sheet for details. 18.3 program write protection bits (pwp) the pic32 families of devices include write protection features, which prevent des ignated boot and program flash regions from being erased or written during program execution. in pic32mx devices, write protection is implemented in configuration memory by the device configuration words, while in pic32mz ec devices, this feature is implemented through special function registers (sfrs) in the flash controller. when write protection is implemented by device configuration words, the write protection register should only be written when all boot and program flash memory has been prog rammed. refer to the ?special features? chapter in the specific device data sheet for details. if write protection is implemented using sfrs, certain steps may be required during initialization of the device by the external programmer prior to programming flash regions. refer to the ?flash program memory? chapter in the specific device data sheet for details. note: once code protection is enabled, the flash memory can no longer be read and can only be disabled by an external pro- grammer using the chip erase command ( mchp_erase ). ? 2007-2013 microchip technology inc. ds61145l-page 55 pic32 19.0 tap controllers table 19-1: mchp tap instructions 19.1 microchip tap controllers (mtap) 19.1.1 mtap_command instruction mtap_command selects the mchp command shift register. see ta b l e 1 9 - 2 for available commands. 19.1.1.1 mchp_status instruction mchp_status returns the 8-bit status value of the microchip tap controller. table 19-3 shows the format of the status value returned. 19.1.1.2 mchp_assert_rst instruction mchp_assert_rst performs a persistent device reset. it is similar to asserting and holding mclr . its associated status bit is devrst. 19.1.1.3 mchp_de_assert_rst instruction mchp_de_assert_rst removes the persistent device reset. it is similar to de-asserting mclr . its associated status bit is devrst. 19.1.1.4 mchp_erase instruction mchp_erase performs a chip erase . the chip_ erase command sets an internal bit that requests the flash controller to perform the erase. once the controller becomes busy, as indicated by fcbusy (status bit), the internal bit is cleared. 19.1.1.5 mchp_flash_enable instruction mchp_flash_enable sets the faen bit, which con- trols processor accesses to the flash memory. the faen bit?s state is returned in the field of the same name. this command has no effect if cps = 0 . this command requires a nop to complete. 19.1.1.6 mchp_flash_disable instruction mchp_flash_disable clears the faen bit which controls processor accesses to the flash memory. the faen bit?s state is returned in the field of the same name. this command has no effect if cps = 0 . this command requires a nop to complete. 19.1.2 mtap_sw_mtap instruction mtap_sw_mtap switches the tap in struction set to the mchp tap instruction set. 19.1.3 mtap_sw_etap instruction mtap_sw_etap effectively switches the tap instruction set to the ejtag tap instruction set. it does this by holding the ejtag tap controller in the run test/idle state until a mtap_sw_etap instruction is decoded by the mchp tap controller. 19.1.4 mtap_idcode instruction mtap_idcode returns the value stored in the devid register. command value description mtap_command 5?h0x07 tdi and tdo connected to mchp command shift register (see ta b l e 1 9 - 2 ). mtap_sw_mtap 5?h0x04 switch tap controller to mchp tap controller. mtap_sw_etap 5?h0x05 switch tap controller to ejtag tap controller. mtap_idcode 5?h0x01 select chip identification data register. note: this command is not required for pic32mz ec family devices. note: this command is not required for pic32mz ec family devices. pic32 ds61145l-page 56 ? 2007-2013 microchip technology inc. table 19-2: mtap_command dr commands table 19-3: mchp status value table 19-4: ejtag tap instructions command value description mchp_status 8?h0x00 nop and return status. mchp_assert_rst 8?h0xd1 requests the reset controller to assert device reset. mchp_de_assert_rst 8?h0xd0 removes the request for device reset, which causes the reset controller to de-assert device rese t if there is no other source requesting reset (i.e., mclr ). mchp_erase 8?h0xfc cause the flash controll er to perform a chip erase. mchp_flash_enable (1) 8?h0xfe enables fetches and loads to the flash (from the processor). mchp_flash_disable (1) 8?h0xfd disables fetches and loads to the flash (from the processor). note 1: this command is not required for pic32mz ec family devices. bit range bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7:0 cps 0 nvmerr (1) 0 cfgrdy fcbusy faen (2) devrst bit 7 cps: code-protect state bit 1 = device is not code-protected 0 = device is code-protected bit 6 unimplemented: read as ? 0 ? bit 5 nvmerr: nvmcon status bit (1) 1 = an error occurred during nvm operation 0 = an error did not occur during nvm operation bit 4 unimplemented: read as ? 0 ? bit 3 cfgrdy: code-protect state bit 1 = configuration has been read and cp is valid 0 = configuration has not been read bit 2 fcbusy: flash controller busy bit 1 = flash controller is busy (erase is in progress) 0 = flash controller is not busy (either er ase has not started or it has finished) bit 1 faen: flash access enable bit (2) this bit reflects the state of cfgcon.faen. 1 = flash access is enabled 0 = flash access is disabled (i.e., processor accesses are blocked) bit 0 devrst: device reset state bit 1 = device reset is active 0 = device reset is not active note 1: this bit is not implemented in pic32m x320/340/360/420/440/460 devices. 2: this bit is not implemented in pic32mz ec family devices. command value description etap_address 5?h0x08 select address register. etap_data 5?h0x09 select data register. etap_control 5?h0x0a select ejtag control register. etap_ejtagboot 5?h0x0c set ejtagbrk, proben and probtrap to ? 1 ? as the reset value. etap_fastdata 5?h0x0e selects the data and fastdata registers. ? 2007-2013 microchip technology inc. ds61145l-page 57 pic32 19.2 ejtag tap controller 19.2.1 etap_address command etap_address selects the address register. the read-only address register provides the address for a processor access. the value read in the register is valid if a processor access is pending, otherwise the value is undefined. the two or three least significant bytes (lsbs) of the register are used with t he psz field from the ejtag control register to indicate the size and data position of the pending processor access transfer. these bits are not taken directly from the address referenced by the load/store. 19.2.2 etap_data command etap_data selects the data register. the read/write data register is used for op code and data transfers during processor accesses. the value read in the data register is valid only if a pr ocessor access for a write is pending, in which case the data register holds the store value. the value written to the data register is only used if a processor access for a pending read is finished afterwards; in which case, the data value written is the value for the fetch or load. this behavior implies that the data register is not a memory location where a previously written value can be read afterwards. 19.2.3 etap_control command etap_control selects the control register. the ejtag control register (ecr) handles processor reset and soft reset indication, debug mode indication, access start, finish and size, and read/write indication. the ecr also provides the following features: ? controls debug vector location and indication of serviced processor accesses ? allows a debug interrupt request ? indicates a processor low-power mode ? allows implementation-dependent processor and peripheral resets 19.2.3.1 ejtag control register (ecr) the ejtag control register (see register 19-1 ) is not updated/written in the update-dr state unless the reset occurred; that is r occ (bit 31) is either already ? 0 ? or is written to ? 0 ? at the same time. this condition ensures proper handling of processor accesses after a reset. reset of the processor can be indicated through the r occ bit in the tck domain a number of tck cycles after it is removed in the processor clock domain in order to allow for proper synchronization between the two clock domains. bits that are read/write (r/w) in the register return their written value on a subsequent read, unless other behavior is defined. internal synchronization ensures that a written value is updated for reading immediately afterwards, even when the tap controller takes the shortest path from the update-dr to capture-dr state. pic32 ds61145l-page 58 ? 2007-2013 microchip technology inc. register 19-1: ecr: ejtag control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r-0 r-0 u-0 u-0 u-0 u-0 u-0 rocc psz<1:0> ? ? ? ? ? 23:16 r-0 r-0 r-0 r/w-0 r-0 r/w-0 u-0 r/w-0 vped doze halt perrst prnw pracc ? prrst 15:8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 proben probtrap ?ejtagbrk ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r-0 u-0 u-0 u-0 ? ? ? ? dm ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 see note 1 bit 28-24 unimplemented: read as ? 0 ? bit 23-19 see note 1 bit 18 pracc: pending processor access and control bit this bit indicates a pending processor access and cont rols finishing of a pending processor access. a write of ? 0 ? finishes processor access if pending. a write of ? 1 ? is ignored. a successful fastdata access will clear this bit. 1 = pending processor access 0 = no pending preprocessor access bit 17 unimplemented: read as ? 0 ? bit 16 see note 1 bit 15 proben: processor access service control bit this bit controls where the probe handles accesses to the dmseg segment through servicing of processor accesses. 1 = probe services processor accesses 0 = probe does not service processor access bit 14 probtrap: debug exception vector control location bit this bit controls the location of the debug exception vector. 1 = 0xff200200 0 = 0xbfc00480 bit 13 unimplemented: read as ? 0 ? bit 12 ejtagbrk: debug interrupt exception request bit this bit requests a debug interrupt exception to the processor when this bit is written as ? 1 ?. a write of ? 0 ? is ignored. 1 = a debug interrupt exception request is pending 0 = a debug interrupt exception request is not pending bit 11-4 unimplemented: read as ? 0 ? bit 3 see note 1 bit 2-0 unimplemented: read as ? 0 ? note 1: for descriptions of these bits, please refer to t he ejtag control register field descriptions in the ?ejtag specification? (md00047), which is available from mips technologies, inc. ( www.mips.com ). ? 2007-2013 microchip technology inc. ds61145l-page 59 pic32 19.2.4 etap_ejtagboot command the etap_ejtagboot command causes the processor to fetch code from the debug exception vector after a reset. this allows the programmer to send instructions to the pr ocessor to execute, instead of the processor fetching them from the normal reset vector. the reset value of the ejtagbrk, probtrap, and probe bits follows the setting of the internal ejtagboot indication. if the ejtagboot instruction has been given, and the internal ejtagboot indicati on is active, then the reset value of the three bits is set (? 1 ?), otherwise the reset value is clear (? 0 ?). the results of setting these bits are: ? setting the ejtagbrk causes a debug interrupt exception to be requested right after the processor reset from the ejtagboot instruction ? the debug handler is executed from the ejtag memory because probtrap is set to indicate debug vector in ejtag memory at 0xff200200 ? service of the proce ssor access is indicated because proben is set with this configuration in place, an interrupt exception will occur and the processor will fetch the handler from the dmseg at 0xff200200. since proben is set, the processor will wait for the instruction to be provided by the probe. 19.2.5 etap_fastdata command the etap_fastdata command provides a mechanism for quickly transferring data between the processor and the probe. the width of the fastdata register is one bit. during a fast data access, the fastdata register is written and read (i.e., a bit is shifted in and a bit is shifted out). during a fast data access, the fastdata register value shifted in specifies whether the fast data access should be completed or not. the value shifted out is a flag that indicates whether the fast data access was successful or not (if completion was requested). the fastdata access is used for efficient block transfers between the dmseg segment (on the probe) and target memory (on the processor). an ?upload? is defined as a sequence that the processor loads from target memory and stores to the dmseg segment. a ?download? is a sequence of processor loads from the dmseg segment and stores to target memory. the ?fastdata area? specifies the legal range of dmseg segment addresses (0xff200000 to 0xff20000f) that can be used for uploads and downloads. the data and fastdata registers (selected with the fastdata instruction) allow efficient completion of pending fastdata area accesses. during fastdata uploads and downloads, the processor will stall on accesses to the fastdata area. the pracc (processor access pending bit) will be ? 1 ? indicating the probe is required to complete the access. both upload and download accesses are attempted by shifting in a zero spracc value (to request access completion) and shifting out spracc to see if the attempt will be successful (i .e., there was an access pending and a legal fastdata area address was used). downloads will also shift in the data to be used to satisfy the load from the dmseg segment fastdata area, while uploads will shift out the data being stored to the dmseg segment fastdata area. as noted above, two conditions must be true for the fastdata access to succeed. these are: ? pracc must be ? 1 ? (i.e., there must be a pending processor access) ? the fastdata operation must use a valid fastdata area address in the dmseg segment (0xff200000 to 0xff20000f) pic32 ds61145l-page 60 ? 2007-2013 microchip technology inc. 20.0 ac/dc characteristics and timing requirements table 20-1: ac/dc characteristics and timing requirements standard operating conditions operating temperature: 0oc to +70oc. programming at +25oc is recommended. param. no. symbol characteristic min. max. units conditions d111 v dd supply voltage during programming ? ? v see note 1 d113 i ddp supply current during programming ? ? ma see note 1 d114 i peak instantaneous peak current during start-up ? ? ma see note 1 d031 v il input low voltage ? ? v see note 1 d041 v ih input high voltage ? ? v see note 1 d080 v ol output low voltage ? ? v see note 1 d090 v oh output high voltage ? ? v see note 1 d012 c io capacitive loading on i/o pin (pgedx) ? ? pf see note 1 d013 c f filter capacitor value on v cap ?? ? f see note 1 p1 t pgc serial clock (pgecx) period 100 ? ns ? p1a t pgcl serial clock (pgecx) low time 40 ? ns ? p1b t pgch serial clock (pgecx) high time 40 ? ns ? p6 t set 2v dd ?? setup time to mclr ? 100 ? ns ? p7 t hld 2 input data hold time from mclr ? 500 ? ns ? p9a t dly 4 pe command processing time 40 ? ? s? p9b t dly 5 delay between pgedx ?? by the pe to pgedx released by the pe 15 ? ? s? p11 t dly 7 chip erase time ? ? ms see note 1 p12 t dly 8 page erase time ? ? ms see note 1 p13 t dly 9 row programming time ? ? ms see note 1 p14 t r mclr rise time to enter icsp? mode ? 1.0 ? s? p15 t valid data out valid from pgecx ? 10 ? ns ? p16 t dly 8 delay between last pgecx ? and mclr ? 0?s ? p17 t hld 3mclr ?? to v dd ? ? 100 ns ? p18 t key 1 delay from first mclr ?? to first pgecx ?? for key sequence on pgedx 40 ? ns ? p19 t key 2 delay from last pgecx ?? for key sequence on pgedx to second mclr ?? 40 ? ns ? p20 t mclrh mclr high time ? 500 s ? note 1: refer to the ?electrical ch aracteristics? chapter in the specific device data sheet for the minimum and maximum values fo r this parameter. ? 2007-2013 microchip technology inc. ds61145l-page 61 pic32 appendix a: pic32 flash memory map figure a-1: flash memory map appendix b: hex file format flash programmers process the standard hexadecimal (hex) format used by the mi crochip development tools. the format supported is the intel ? hex32 format (inhx32). please refer to section 1.75 ?hex file formats? in the ?mpasm? assembler, mplink? object linker, mplib? object librarian user?s guide? (ds33014) for more information about hex file formats. the basic format of the hex file is: :bbaaaatthhhh...hhhhcc each data record begins with a 9-character prefix and always ends with a 2-charac ter checksum. all records begin with ? : ?, regardless of the format. the individual elements are described below. ? bb ? is a two-digit hexadecimal byte count representing the number of data bytes that appear on the line. divide this number by two to get the number of words per line. ? aaaa ? is a four-digit hexadecimal address representing the starting address of the data record. format is high byte first followed by low byte. the address is doubled because this format only supports 8 bits. divide the value by two to find the real device address. ? tt ? is a two-digit record type that will be ?00? for data records, ?01? for end-of-file records and ?04? for extended-address record. ? hhhh ? is a four-digit hexadecimal data word. format is low byte followed by high byte. there will be bb /2 data words following tt . ? cc ? is a two-digit hexadecimal checksum that is the 2?s complement of the sum of all the preceding bytes in the line record. because the intel hex file format is byte-oriented, and the 16-bit program counter is not, program memory sections require special treatment. each 24-bit program word is extended to 32 bits by inserting a so- called ?phantom byte?. each program memory address is multiplied by 2 to yield a byte address. as an example, a section that is located at 0x100 in program memory will be represented in the hex file as 0x200. the hex file will be produced with the following contents: :020000040000fa :040200003322110096 :00000001ff notice that the data record (line 2) has a load address of 0200, while the source code specified address 0x100. note also that the data is represented in ?little-endian? format, meaning the least significant byte appears first. the phantom byte appears last, just before the checksum. boot page 0 boot page 1 boot page 2 debug page configuration words (4 x 32 bits) 0x1f000000 0x1f001fff 0x1f002ff0 0x1f002fff 0x1d000000 program flash memory 0x1d007fff pfm bfm note: the memory map shown is for reference only. refer to the ?memory organization? chapter in the specific device data sheet for the memory map for your device. pic32 ds61145l-page 62 ? 2007-2013 microchip technology inc. appendix c: revision history revision a (august 2007) this is the initial released version of the document. revision b (february 2008) update records for this revision are not available. revision c (april 2008) update records for this revision are not available. revision d (may 2008) update records for this revision are not available. revision e (july 2009) this version of the document includes the following additions and updates: ? minor changes to style and formatting have been incorporated throughout the document ? added the following devices: - pic32mx565f256h - pic32mx575f512h - pic32mx675f512h - pic32mx795f512h - pic32mx575f512l - pic32mx675f512l - pic32mx795f512l ? updated mclr pulse line to show active-high (p20) in figure 7-1 ? updated step 7 of table 11-1 to clarify repeat of the last instruction in the step ? the following instructions in table 13-1 were updated: - seventh, ninth and eleventh instructions in step 1 - all instructions in step 2 - first instruction in step 3 - third instruction in step 4 ? added the following devices to table 17-1: - pic32mx565f256h - pic32mx575f512h - pic32mx575f512l - pic32mx675f512h - pic32mx675f512l - pic32mx795f512h - pic32mx795f512l ? updated address values in table 17-2 revision e (july 2009) (continued) ? added the following devices to table 17-5: - pic32mx565f256h - pic32mx575f512h - pic32mx675f512h - pic32mx795f512h - pic32mx575f512l - pic32mx675f512l - pic32mx795f512l ? added notes 1-3 and the following bits to the devcfg - device config uration word summary and the devcfg3: device configuration word 3 (see table 18-1 and register ): -fvbusio - fusbidio - fcanio -fethio - fmiien -fpbdiv<1:0> - fjtagen ? updated the devid summary (see table 18-1) ? updated icesel bit description and added the fjtagen bit in devcfg0: device configuration word 0 (see register 16-1) ? updated devid: device and revision id register ? added device ids and revision table (table 18-4) ? added mclr high time (parameter p20) to table 20-1 ? added appendix b: ?hex file format? and appendix d: ?revision history? revision f (april 2010) this version of the document includes the following additions and updates: ? the following global bit name changes were made: - nvmwr renamed as wr - nvmwren renamed as wren - nvmerr renamed as wrerr - fvbusio renamed as fvbusonio - fupllen renamed as upllen - fupllidiv renam ed as upllidiv - poscmd renamed as poscmod ? updated the pic32mx family data sheet references in the fourth paragraph of section 2.0 ?programming overview? ? updated the note in section 5.2.2 ?2-phase icsp? ? updated the initiate flash row write op codes and instructions (see steps 4, 5 and 6 in table 13-1) ? 2007-2013 microchip technology inc. ds61145l-page 63 pic32 revision f (april 2010) (continued) ? added the following devices: - pic32mx534f064h - pic32mx534f064l - pic32mx564f064h - pic32mx564f064l - pic32mx564f128h - pic32mx564f128l - pic32mx575f256l - pic32mx664f064h - pic32mx664f064l - pic32mx664f128h - pic32mx664f128l - pic32mx675f256h - pic32mx675f256l - pic32mx695f512h - pic32mx605f512l - pic32mx764f128h - pic32mx764f128l - pic32mx775f256h - pic32mx775f256l - pic32mx775f512h - pic32mx775f512l revision g (august 2010) this revision of the document includes the following updates: ? updated step 3 in table 11-1: download the pe ? minor corrections to formatting and text have been incorporated throughout the document revision h (april 2011) this version of the document includes the following additions and updates: ? updates to formatting and minor typographical changes have been incorporated throughout the document ? the following devices were added: - pic32mx110f016b - pic32mx110f016c - pic32mx110f016d - pic32mx120f032b - pic32mx120f032c - pic32mx120f032d - pic32mx210f016b - pic32mx210f016c - pic32mx210f016d - pic32mx220f032b - pic32mx220f032c - pic32mx220f032d ? the following rows were added to table 17-1: - pic32mx1x0 - pic32mx2x0 ? added a new sub section section 17.4.6 ?checksum values while device is code- protected? ? removed register 18-1 through register 18-5. ? removed table 17-2 ? removed section 17.5 ?checksum for pic32 devices? and its sub sections ? the flash program memory write-protect ranges table was removed (formerly table 18-4) ? added devcfg locations for pic32mx1x0 and pic32mx20x devices only (see table 18-3) ?in section 18.0 ?configuration memory and device id? , removed table 18-1 and updated table 18-2: devid summary as table 18-1 ? added the nvmerr bit to the mchp status value table (see table 19-3) ? the following silicon revision and revision id are added to table 18-4: - 0x5 - b6 revision - 0x1 - a1 revision ? added a note to the flash memory map (see figure a-1) ? added appendix c: ?flash program memory data sheet clarification? revision j (august 2011) this revision includes the following updates: ? all occurrences of v core /v cap have been changed to v cap ? updated the fourth paragraph of section 2.0 ?programming overview? ? removed the column, pr ogrammer pin name, from the 2-wire interface pins table and updated the pin type for mclr (see table 4-2) ? added the following new devices to the code memory size table (see table 5-1) and the device ids and revision table (see table 18-4): - pic32mx130f064b - pic32mx130f064c - pic32mx130f064d - pic32mx150f128b - pic32mx150f128c - pic32mx150f128d - pic32mx230f064b - pic32mx230f064c - pic32mx230f064d - pic32mx250f128b - pic32mx250f128c - pic32mx250f128d ? added row size and page size columns to the code memory size table (see table 5-1) note: the revision history in this document intentionally skips from revision h to revision j to avoid confusing the uppercase letter ?i? (ey) with the lowercase letter ?l? (el). pic32 ds61145l-page 64 ? 2007-2013 microchip technology inc. revision j (august 2011) (continued) ? updated the pgcx signal in entering enhanced icsp mode (see figure 7-1) ? updated the erase device block diagram (see figure 9-1) ? added a new step 4 to the process to erase a target device in section 9.0 ?erasing the device? ? updated the mclr signal in 2-wire exit test mode (see figure 15-2) ? updated the pe command set with the following commands and modified note 2 (see table 16-2): - program_cluster - get_deviceid - change_cfg ? added a second note to section 16.2.11 ?get_crc command? ? updated the address and length descriptions in the program_cluster format (see table 16-13) ? added a note after the change_cfg response (see figure 16-27) ? updated the devcfg0 and devcfg1 values for all pic32mx1xx and all pic32mx2xx devices in table 17-1 ? the following changes were made to the ac/dc characteristics and timing requirements (table 20-1): - updated the min. value for parameter d111 (v dd ) - added parameter d114 (i peak ) - removed parameters p2 , p3, p4, p4a, p5, p8 and p10 ? removed appendix c: ?flash program memory data sheet clarification? ? minor updates to text and formatting were incorporated throughout the document revision k (july 2012) this revision includes the following updates: ? all occurrences of pgc and pgd were changed to: pgec and pged, respectively ? updated section 1.0 ?device overview? with a list of all major topics in this document ? added section 2.3 ?data sizes? ? updated section 4.0 ?connecting to the device? ? added note 2 to connections for the on-chip regulator (see figure 4-2) ? added note 2 to the 4-wire and 2-wire interface pins tables (see table 4-1 and table 4-2) ? updated section 7.0 ?entering 2-wire enhanced icsp mode? ? updated entering serial execution mode (see figure 10-1) ? updated step 11 in section 10.2 ?2-wire interface? ? updated section 12.2 ?with the pe? ? updated step 3 in initiate flash row write op codes (see table 13-1) ? updated step 1 in verify device op codes (see table 14-1) ? updated the interval in section 15.1 ?4-wire interface? and section 15.2 ?2-wire interface? ? added a note regarding the pe location in section 16.0 ?the programming executive? ? added references to the operand field throughout section 16.2 ?the pe command set? ? updated the program command algorithm (see figure 16-9) ? updated the mask values for all pic32mx1xx and pic32mx2xx devices, and devcfg3 for all devices (see table 17-1) ? updated the dcr value (see section 17.4.3 ?calculating for ?dcr? in the checksum formula? and table 17-2) ? updated the checksum calculation process (see example 17-1) ? added these new devices to the code memory size table (see table 5-1) and the device ids and revision table (see table 18-4): ? added a note to section 18.2 ?device code protection bit (cp)? ? added the ejtag control register (see register 19-1) ? updated section 19.2.4 ?etap_ejtagboot command? ? ac/dc characteristics and timing requirements updates (see table 20-1): - removed parameter d112 - replaced notes 1 and 2 with a new note 1 - updated parameters d111, d113, d114, d031, d041, d080, d090, d012, d013, p11, p12, and p13 ? minor updates to text and formatting were incorporated through the document - pic32mx420f032h - pic32mx450f 128l - pic32mx330f064h - pic32mx440f 256h - pic32mx330f064l - pic32mx450f256h - pic32mx430f064h - pic32mx450f 256l - pic32mx430f064l - pic32mx460f256l - pic32mx340f128h - pic32mx340f 512h - pic32mx340f128l - pic32mx360f512h - pic32mx350f128h - pic32mx370f 512h - pic32mx350f128l - pic32mx370f512l - pic32mx350f256h - pic32mx440f 512h - pic32mx350f256l - pic32mx460f512l - pic32mx440f128h - pic32mx470f 512h - pic32mx440f128l - pic32mx470f512l - pic32mx450f128h ? 2007-2013 microchip technology inc. ds61145l-page 65 pic32 revision l (january 2013) this revision includes the following updates: ? the following sections were added or updated: - section 2.1 ?devices with dual flash panel and dual boot regions? (new) - section 4.3 ?power requirements? - section 13.0 ?initiating a flash row write? - section 16.1.1 ?2-wire icsp ejtag rate? ? updated the device configuration register mask values (see table 17-1 ) ? the following devices were added to the code memory size table and the device ids and revision table (see ta b l e 5 - 1 and ta b l e 1 8 - 4 ): ? note 3 and note 4 and the get_checksum and quad_word_prgm commands were added to the pe command set (see table 16-2 ) ? added section 16.2.15 ?get_checksum command? ? added section 16.2.16 ?quad_word_program command? ? updated all addresses in devcfg locations (see table 18-1 and ta b l e 1 8 - 2 ) ? added configuration word locations for pic32mz ec family devices (see table 18-3 ) ? updated section 18.2 ?device code protection bit (cp)? ? updated section 18.3 ?program write protection bits (pwp)? ? all references to test mode were updated to programming mode throughout the document ? minor updates to text and formatting were incorporated through the document - pic32mz0256ece064 - pic32mz1024ecf064 - pic32mz0256ece100 - pic32mz1024ecf100 - pic32mz0256ece124 - pic32mz1024ecf124 - pic32mz0256ece144 - pic32mz1024ecf144 - pic32mz0256ecf064 - pic32mz1024ecg064 - pic32mz0256ecf100 - pic32mz1024ecg100 - pic32mz0256ecf124 - pic32mz1024ecg124 - pic32mz0256ecf144 - pic32mz1024ecg144 - pic32mz0512ece064 - pic32mz1024ech064 - pic32mz0512ece100 - pic32mz1024ech100 - pic32mz0512ece124 - pic32mz1024ech124 - pic32mz0512ece144 - pic32mz1024ech144 - pic32mz0512ecf064 - pic32mz2048ecg064 - pic32mz0512ecf100 - pic32mz2048ecg100 - pic32mz0512ecf124 - pic32mz2048ecg124 - pic32mz0512ecf144 - pic32mz2048ecg144 - pic32mz1024ece064 - pic32mz2048ech064 - pic32mz1024ece100 - pic32mz2048ech100 - pic32mz1024ece124 - pic32mz2048ech124 - pic32mz1024ece144 - pic32mz2048ech144 pic32 ds61145l-page 66 ? 2007-2013 microchip technology inc. notes: ? 2007-2013 microchip technology inc. ds61145l-page 67 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademar ks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2007-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-856-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds61145l-page 68 ? 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